This page should contain information about the Focal project, especially about the interfacing from the Mimosa chips to the readout electronics.
- preliminary user manual of Phase1
- BSDL file of Phase1, which can be used for JTAG test, such as with an XJTAG module.
- SVF file for pattern-only mode test of Phase1, Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.
The adapterboard and fan-out boards provide LVDS interfaces and JTAG interfaces between the Control and Read-out board and the Mimosa ASICs. Here is the schematics of the boards.
- Spartan6 FPGA type: XC6SLX150-FGG676, speed-grade: 3
- Examples of user constraint files for Spartan6 FPGAs: U1 , U2
- EXamples of VHDL entity definations for Spartan6 FPGAs: U1 , U2
Control and Readout board
The idea is to use a Xilinx Virtex 6 development board as a first prototype. The board will run Petalinux, and some software to access the firmware registers. A software framework for the TPC detector is to be adapted for the use on the Virtex 6 board and Petalinux.
The VHDL counterpart is to be found here: http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-fw/trunk/messagebuffer/
- Petalinux documentation: petalinux_sdk