Busy Box and related

Overview

Block diagram BusyBox

ALICE is one of four large detectors situated at the collision points in the Large Hadron Collider (LHC) at CERN. The BusyBox is used by four of ALICE’s sub-detectors: Time Projection Chamber (TPC), Photon Spectrometer (PHOS), Forward Multiplicity Detector (FMD) and Electromagnetic Calorimeter (EMCal)

Triggers initiate data readout from ALICE’s sub-detectors and are received by the DCS board via an optical cable interface. The triggers and associated data are routed from the TTCrx ASIC on the DCS board to the BusyBox FPGA(s). Here, the L1a and Serial B line raw data is decoded by the Trigger Receiver firmware module.

Every time a trigger sequence starts the Fee starts buffering data, i.e. a buffer in the Fee is used. A valid trigger sequence ends with an L2a trigger and the event data along with the event ID is sent to the D-RORCs.

The purpose of BusyBox is to let the Central Trigger Processor (CTP) know when the Fee’s buffers are full by asserting a busy signal which prevents further issuing of triggers. The BusyBox and D-RORCs receives a unique event ID from the Fee after an event. After a valid trigger sequence ends the BusyBox will ask the D-RORCs if they have received the same event ID as the BusyBox did. If they do not reply with the same ID it means data has not been shipped from the Fee to the D-RORC, hence, the buffer in the Fee still holds event data.

The Fee buffers can hold 4 or 8 events and the BusyBox keeps track of free buffers. The busy is asserted if the buffers are full.

Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.

The BusyBoxes are located in the DAQ counting rom.

BusyBox Hardware tests at UiB

In one of our labs at UiB we have a setup for testing new BusyBox firmware in hardware before releasing it. The setup features a full readout chain for one channel of the ALICE TPC.

Components in LAB setup :

Local Trigger Crate (LTU)
Readout Control Unit (RCU) with Front End Cards (FEC)
Local Data Concentrator (LDC) with 3 DAQ ReadOut Receiver Cards (DRORC) and date software.
BusyBox with 2 FPGAs but only 1U rack.

BusyBox Firmware

Busy Box Registers

See BusyBox Registers for latest updated information on firmware registers.

Source Code Repositories

BusyBox FPGAs

There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. Alternatively fpga2 can be prgrammed with 'dummy.bit'.

Compiled BusyBox Firmware Versions

Revision 31

Using Trigger Receiver Module v.1.3 Now handles orphan L2 Accept triggers by looking at the payload bit in the event info.

Download

busybox_fpga1_solo.bit busybox_fpga1.bit busybox_fpga2.bit

Versioning

The busybox version number is now the same as the revision number of the source in SVN it was generated from. This should make it possible to get the original source files for any programming file. A register for the version number exists in the ctrl_regs module.

Revision 41

Non functional FW changes

Signal names used globally in the design have been renamed: clocka => clk200, clockb => clk40, areset => rst40 /rst200
All processes in all VHDL files used in the design, except for the trigger receiver module, have been updated to implement a synchronous reset.
Since a stable clock is required for to perform a proper synchronous reset, a new module that implements reset logic has been added to the design in busylogic_top module. The reset logic will assert reset for as long as the DCM has not locked on the incoming clock. The reset will be released synchronously about 10 cycles after the DCM has asserted its locked signal.
Since the actual clock of the LHC is 40.08 MHz and not the nominal 40 MHz the constraints for the implementation tools has been set 41 MHz. (85 degrees celsius, 41 MHz, 1.14 V)

Event verification module (event_validator_top)

This module has been modified so that the event ID queue now also contains the event info and event errors in addition to the event ID. The event info and event errors for the newest and current events are made available as registers. This extra info about the trigger sequence can be helpful when debugging. The event info contains the payload bit which is forwarded to the busy_controller. It is used in the process of calculating used MEBs.

Serial decoder

The serial decoder has been changed to reduce the resource usage. This module is replicated many times in the design so any improvement is significant. The old architecture used a shift register long enough to hold all bit-samples for one data frame (about 100 samples). The frame was captured in one go when a valid capture condition was found in the samples. The new architecture uses shorter shift register (about 10 samples) and only looks at a few samples at a time. Once the start condition is found it will capture the bits of the frame sequentially, bit by bit. The new architecture of this module has led to great improvements in resource usage. BusyBox firmware with 96 channels used to occupy approximately 96% of the FPGA. This number has been reduced to approximately 66%. Reduced resource usage makes it easier for the implementation tools to generate the programming file and it should also reduce the TDP of the device under operation.

DCS arbiter and address decoder

The architecture of this module has been updated to make it more readable and to register inputs such as address and data from the DCS bus master.

Registers

Extra registers has been added:

Number of implemented channels. This number is actually the same as the generic g_num_channels.
Current Trigger Event Info
Current Trigger Event Error
Newest Trigger Event Info
Newest Trigger Event Error

Download

Revision 49

Free Buffer counting scheme

The buffer counter is now incremented on L2A only, and decremented as before on Valid Event signal (meaning that all DRORCs have received the current event). In previous versions the buffer counter was incremented on L1A and decremented on L2R, time-outs and valid events.

Trigger burst interlock

A new feature has been added. The purpose is to prevent long bursts of trigger. A maximum number of triggers in a burst can be defined in the burst size register. A counter ("leaky bucket") counts up until a the maximum value is reached for every L0 trigger received. It counts down on pulses from a pulse generator until minimum (0). The interval of these "leak-pulses" is programmable from 0 to 200 ms in 10 us steps. We are busy when the "leaky bucket" is full. This feature can be disabled by setting the burst size to 0 (default value).

Two new registers are added:

Burst Size (address 0x2017)
Burst Leak Time (address (0x2018)

A new status bit has been added to the Busy condition register to indicate Burst Bucket Full as the reason for Busy State.

DCS board firmware for BusyBox

The DCS board in the BusyBox uses special firmware. See Electronics for the TPC

Generating FPGA configuration files from source code

Check out the desired revision from the SVN repository.
Navigate to .../busybox_firmware/trunk/ISE_projects
Run the TCL script named bbiseproject.tcl with Xilinx' TCL interpreter. The script takes three commandline arguments :
- fpga_version - see #BusyBox FPGAs
- source_dir - where the source code is located. Including constraints and cores.
- project_dir - location where project is created. Note folder has to exist and should not already contain an ISE project.
Example: D:\busybox_firmware\trunk\ISE_projects>xtclsh bbiseproject.tcl busybox_fpga1_solo ..\source test
Generate the cores with CoreGen (If it not already done)
This can be done by using the CoreGen GUI or by invoking coregen in batch mode from the commandline. To use the GUI; start coregen while in .../busybox_firmware/trunk/source/cores.

For batch mode : .../busybox_firmware/trunk/source/cores/coregen -b 'core'.xco replace 'core' with real name for all *.xco-files.

Example with DOS for loop: D:\busybox_firmware\trunk\source\cores>FOR %i IN (*.xco) DO coregen -b %i
Open the project with ISE Project Navigator.
Run process 'Generate Programming File'