FOCAL - Forward Calorimeter: Difference between revisions
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from the Mimosa chips to the readout electronics. | from the Mimosa chips to the readout electronics. | ||
== Overview == | == Overview == | ||
[[Media:Focal readout.pdf|Simple description of the Alice Focal readout electronics]]. | |||
== Mimosa chips == | == Mimosa chips == | ||
* [[Media:PH1-UserMan-20080916.pdf|preliminary user manual of Phase1]] | |||
* [[Media:mimosa.bsd.txt|BSDL file of Phase1]], which can be used for JTAG test, such as with an XJTAG module. | |||
* [[Media:pattern_test.svf.txt|SVF file for pattern-only mode test of Phase1]], Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal. | |||
== Readout electronics == | == Readout electronics == | ||
=== Adapterboard === | === Adapterboard /Fanoutboard === | ||
The schematics of the | The adapterboard and fan-out boards provide LVDS interfaces and JTAG interfaces between the Control and Read-out board and the Mimosa ASICs. Here is [[Media:Focal_read-out_board_schematics.pdf|the schematics of the boards]]. | ||
* Spartan6 FPGA type: [http://www.xilinx.com/support/documentation/spartan-6.htm XC6SLX150-FGG676, speed-grade: 3] | |||
* Examples of user constraint files for Spartan6 FPGAs: [[Media:U1.ucf.txt| U1 ]],[[Media:U2.ucf.txt| U2 ]] | |||
* EXamples of VHDL entity definations for Spartan6 FPGAs: [[Media:U1.vhdl.txt| U1 ]],[[Media:U2.vhdl.txt| U2 ]] | |||
=== Control and Readout board === | === Control and Readout board === | ||
The idea is to use a Xilinx Virtex 6 development board as a first prototype. The board | The idea is to use a [http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm Xilinx Virtex 6 development board] as a first prototype. The board will run Petalinux, and some software to access the firmware registers. A software framework for the TPC detector is to be adapted for the use on the Virtex 6 board and Petalinux. | ||
*[[Media:ML605.ucf.txt|FPGA user constraint file for Virtex 6 development board]] | |||
==== Firmware ==== | ==== Firmware ==== | ||
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==== Software ==== | ==== Software ==== | ||
* [[Setting Up PetaLinux System]] | |||
Petalinux documentation: | * Petalinux documentation: [http://www.petalogix.com/resources/documentation/petalinux_sdk petalinux_sdk] | ||
[http://www.petalogix.com/resources/documentation/petalinux_sdk] | |||
* [[Get readout box up and running]] | |||
* [[Programming Mimosa chips]] | |||
==Readout software== | |||
[[Report by Tony]] | |||
[[Category:Mikroelektronikk]] | |||
Latest revision as of 14:47, 10 August 2012
This page should contain information about the Focal project, especially about the interfacing from the Mimosa chips to the readout electronics.
Overview
Simple description of the Alice Focal readout electronics.
Mimosa chips
- preliminary user manual of Phase1
- BSDL file of Phase1, which can be used for JTAG test, such as with an XJTAG module.
- SVF file for pattern-only mode test of Phase1, Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.
Readout electronics
Adapterboard /Fanoutboard
The adapterboard and fan-out boards provide LVDS interfaces and JTAG interfaces between the Control and Read-out board and the Mimosa ASICs. Here is the schematics of the boards.
- Spartan6 FPGA type: XC6SLX150-FGG676, speed-grade: 3
- Examples of user constraint files for Spartan6 FPGAs: U1 , U2
- EXamples of VHDL entity definations for Spartan6 FPGAs: U1 , U2
Control and Readout board
The idea is to use a Xilinx Virtex 6 development board as a first prototype. The board will run Petalinux, and some software to access the firmware registers. A software framework for the TPC detector is to be adapted for the use on the Virtex 6 board and Petalinux.
Firmware
The VHDL counterpart is to be found here: http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-fw/trunk/messagebuffer/
Software
- Petalinux documentation: petalinux_sdk