SAMPA MPW1 Registers

Channel specific registers

These are registers specific to each channel. By using a broadcast command, all channels can be written at the same time.

Register name		Address	Type	Default value		Description
K1	[12:0]	0x00	RW	0x00	[12:0]	First pole of the TCFU
K2	[12:0]	0x01	RW	0x00	[12:0]	Second pole of the TCFU
K3	[12:0]	0x02	RW	0x00	[12:0]	Third pole of the TCFU
K4	[12:0]	0x03	RW	0x00	[12:0]	Fourth pole of the TCFU
L1	[12:0]	0x04	RW	0x00	[12:0]	First zero of the TCFU
L2	[12:0]	0x05	RW	0x00	[12:0]	Second zero of the TCFU
L3	[12:0]	0x06	RW	0x00	[12:0]	Third zero of the TCFU
L4	[12:0]	0x07	RW	0x00	[12:0]	Fourth zero of the TCFU
ZSTHR	[19:0]	0x08	RW	0x0A	[9:0]	Zero suppression threshold
			RW	0x00	[19:10]	Zero suppression offset
ZSCFG	[6:0]	0x09	RW	0x02	[1:0]	Glitch filter, minimum accepted pulse
			RW	0x07	[4:2]	Post-samples
			RW	0x03	[6:5]	Pre-samples
VFPED	[19:0]	0x0A	RW	0x00	[9:0]	BC1 Fixed pedestal
			R	0x00	[19:10]	BC1 variable pedestal
CTE	[9:0]	0x0B	RW	0x00	[9:0]	Channel specific noise
PMDTA	[9:0]	0x0C	RW	0x00	[9:0]	Data to be stored in the pedestal memory

These are global registers and does not accept broadcast commands.

Register name		Address	Type	Default value		Description
PMADD	[9:0]	0x0D	RW	0x00	[9:0]	Pedestal memory address
BC2THR	[19:0]	0x0E	RW	0x03	[8:0]	Lower threshold of moving average filter
			RW	0x03	[17:9]	Higher threshold of moving average filter
			RW	0x01	[19:18]	Number of taps in moving average filter
TRCFG	[19:0]	0x0F	RW	0x00	[7:0]	Number of pre-samples (Pretrigger delay), max 191
			RW	0x3FD	[17:8]	Number of samples per event, max 1021
DPCFG	[11:0]	0x10	RW	0x00	[3:0]	BC1 mode, see ALTRO manual
			RW	0x00	[4]	BC1 polarity
			RW	0x07	[6:5]	BC2 pre-samples
			RW	0x07	[10:7]	BC2 post-samples
			RW	0x01	[1]	BC2 moving average filter enable
VACFG	[7:0]	0x11	RW	0x00	[1:0]	Number of neighbors, not in use
			RW	0x01	[3:2]	Number of serial out, see table 1.5
			RW	0x00	[4]	Pedestal mode enabled (zero suppression threshold 0)
			RW	0x01	[5]	Power save mode enabled
			RW	0x00	[6]	TCFU enabled
			RW	0x01	[7]	Continuous mode enabled
BC1THR	[13:0]	0x12	RW	0x03	[4:0]	Lower threshold of variable pedestal filter
			RW	0x03	[9:5]	Higher threshold of variable pedestal filter
			RW	0x01	[13:10]	Number of taps in variable pedestal filter
TRCNT	[15:0]	0x13	R	0x00	[15:0]	Trigger count
HWADD	[4:0]	0x14	R	0x00	[4:0]	Chip address (hardware address)
ERRORS	[5:0]	0x15	R	0x00	[0]	Parity error in received instruction
			R	0x00	[1]	Instruction error
			R	0x00	[2]	Trigger overlap
			R	0x00	[3]	SEU in MMU SM (not implemented)
			R	0x00	[4]	SEU in interface SM (not implemented)
BXCNT	[19:0]	0x16	R	0x00	[19:0]	Bunch crossing counter

These are command registers and can only be written to. The value doesn’t matter as only the access is detected.

Register name	Address	Type	Description
SWTRG	0x1B	W	Software trigger (not implemented)
TRCLR	0x1C	W	Clear trigger counter
ERCLR	0x1D	W	Clear errors
BXCLR	0x1E	W	Clear bunch crossing counter
SRST	0x1F	W	Software reset