User contributions for Yag005

4 December 2017

• 16:4916:49, 4 December 2017 diff hist +1,477‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 16:4916:49, 4 December 2017 diff hist +27‎ N File:S00 1.png ‎ File uploaded with MsUpload current
• 16:4816:48, 4 December 2017 diff hist +27‎ N File:S00 2.png ‎ File uploaded with MsUpload current
• 16:4816:48, 4 December 2017 diff hist +27‎ N File:Led ip 1.png ‎ File uploaded with MsUpload current
• 16:4816:48, 4 December 2017 diff hist +27‎ N File:Led ip 2.png ‎ File uploaded with MsUpload current
• 16:4816:48, 4 December 2017 diff hist +27‎ N File:Led ip 3.png ‎ File uploaded with MsUpload current
• 16:4816:48, 4 December 2017 diff hist +27‎ N File:Led port success.png ‎ File uploaded with MsUpload
• 14:2414:24, 4 December 2017 diff hist 0‎ File:Diagram axi4lite periph added.png ‎ Yag005 uploaded a new version of File:Diagram axi4lite periph added.png current
• 13:4713:47, 4 December 2017 diff hist +27‎ N File:Diagram axi4lite periph added.png ‎ File uploaded with MsUpload
• 13:4413:44, 4 December 2017 diff hist +337‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 13:4413:44, 4 December 2017 diff hist +27‎ N File:Add interfaces axi4lite.png ‎ File uploaded with MsUpload current

28 November 2017

• 15:0215:02, 28 November 2017 diff hist +202‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:4314:43, 28 November 2017 diff hist +2‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:4314:43, 28 November 2017 diff hist +120‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:4314:43, 28 November 2017 diff hist 0‎ File:First block.png ‎ Yag005 uploaded a new version of File:First block.png current
• 14:3814:38, 28 November 2017 diff hist −2‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:3814:38, 28 November 2017 diff hist +2‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:3714:37, 28 November 2017 diff hist +1‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:3614:36, 28 November 2017 diff hist +429‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:3614:36, 28 November 2017 diff hist +27‎ N File:First block.png ‎ File uploaded with MsUpload
• 14:3314:33, 28 November 2017 diff hist +27‎ N File:Create block design.png ‎ File uploaded with MsUpload current
• 14:2814:28, 28 November 2017 diff hist +425‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:2514:25, 28 November 2017 diff hist +27‎ N File:New project default part.png ‎ File uploaded with MsUpload current
• 14:1014:10, 28 November 2017 diff hist +412‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:0214:02, 28 November 2017 diff hist 0‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:0114:01, 28 November 2017 diff hist 0‎ File:New project name.png ‎ Yag005 uploaded a new version of File:New project name.png current
• 14:0014:00, 28 November 2017 diff hist +43‎ Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎No edit summary
• 14:0014:00, 28 November 2017 diff hist 0‎ File:New project name.png ‎ Yag005 uploaded a new version of File:New project name.png
• 13:5713:57, 28 November 2017 diff hist +193‎ N Creating example project with AXI4 Lite peripheral in Xilinx Vivado ‎ Created page with "Tested on Xilinx Vivado 2017.3. Start Vivado Goto: ''File -> New Project -> Next''. For this project we will name it axi4_lite_tutorial_project. File:new_project_name.png|..."
• 13:5713:57, 28 November 2017 diff hist 0‎ File:New project name.png ‎ Yag005 uploaded a new version of File:New project name.png
• 13:5413:54, 28 November 2017 diff hist +27‎ N File:New project name.png ‎ File uploaded with MsUpload
• 13:5013:50, 28 November 2017 diff hist +82‎ FreeRTOS FSBL ‎No edit summary
• 13:4613:46, 28 November 2017 diff hist +4‎ FreeRTOS FSBL ‎No edit summary
• 13:4613:46, 28 November 2017 diff hist +47‎ FreeRTOS FSBL ‎No edit summary
• 13:4613:46, 28 November 2017 diff hist +27‎ N File:Export hardware.png ‎ File uploaded with MsUpload current
• 13:4413:44, 28 November 2017 diff hist +7‎ FreeRTOS FSBL ‎No edit summary
• 13:4213:42, 28 November 2017 diff hist 0‎ N File:Launch SDK.png ‎No edit summary current
• 13:4213:42, 28 November 2017 diff hist +305‎ FreeRTOS FSBL ‎No edit summary
• 13:3313:33, 28 November 2017 diff hist +225‎ N FreeRTOS FSBL ‎ Created page with "Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS. This tutorial assumes you have completed the "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"-t..."
• 13:2313:23, 28 November 2017 diff hist +67‎ FreeRTOS ‎No edit summary
• 13:2113:21, 28 November 2017 diff hist +9‎ FreeRTOS ‎No edit summary
• 13:1913:19, 28 November 2017 diff hist +31‎ N FreeRTOS ‎ Created page with "FSBL First Stage Bootloader"
• 13:1713:17, 28 November 2017 diff hist +48‎ Microelectronics group ‎ →‎Annet
• 13:1513:15, 28 November 2017 diff hist +78‎ N User:Yag005 ‎ Created page with "Master student in microelectronics group. Contact email: yag005@student.uib.no"