Cadence Virtuoso overview
IC design flow using Cadence
We have access to several silicon technologies from different foundries
- 130nm CMOS process from Taiwan Semiconductor Manufacturing: TSMC 130nm process
- 130nm SiGe process from Innovations for High Performance Microelectronics: IHP 130nm process
- 350nm CMOS process from Austria Mikro Systeme: AMS 350nm process
Design entry using schematic capture
- Make sure you have set correct library.
- Make sure you run virtuoso from the same folder as your 'cds.lib'-folder ('~/LIBRARY_VENDOR/')
Simulation
Layout
Helpful stuff
MikroserverSetup - setup for easy connection to the mikroservers and Cadence Virtuoso
Transistor operating point printer - Script to extract transistor operating point parameters after simulation.
DCoperatingparameters - Guide for showing transistor operating points in the schematic
ADEXL-butterfly-curves - Howto make DC butterfly curves easily.