Using the VGA controller with block ram generator and clock wizard

If you want to use the vga controller remember to

copy-paste the vga.txt file and save it as vga.vhd
copy-paste the Nexys4_Master.txt file and save it as Nexys4_Master.xdc

The vga controller is using a BRAM block to store pixel values. Each pixel has 12-bits and number of pixels projected to the screen is 480x640=307200

sw_i(15) -- active high, write enable
sw_i(11 downto 0) -- 12-bits for colour changing the screen

CREATING NEW PROJECT

Press create new project

Press next on the first window that pops up, then you can choose were you want to store your project, click next.

Choose RTL project and click next

Add your VHDL file if you have one, if you don’t you can add the VGA-controller file just to make sure that everything works properly. Click next

Click next

Add the Nexys4_Master.xdc , this will connect all your I/O, LED, SW etc.

Choose the xca100tcsg324-1 and click next and then finish.

Vivado will open, now you can make your own VHDL code or you can follow instruction further if you want to use the VGA controller. If you want to make your own code you can skip the IP part and go to generate bitstream to see how you should implement your code on the FPGA.

Adding IP’s, clk generator 25.2MHz and BRAM. Click IP Catalog and then

Search for Clocking Wizard and enter and this will pop up, clocking option should look like this, remember to change the Component name!

Change the output clock to 25.2MHz

Port renaming: use names that explains your component, and click OK

This should pop up, click generate

Adding BRAM, search for bram and enter the Block Memory Generator and this should pop up. Remember component name

Port A Options, write width = 12bits, write depth = 307200=(480*640 pixels projected on screen), then click OK and then generate as before and wait until the synthesis is done.