Busy Box and related/BusyBox Registers

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Busy Box Status and Contol Registers

Address Mode Name Description Default Value
0x0001 RW TX module(15:0) For sending messages to DRORCs.
  • Bit 7:0 is TX data.
  • Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
 0x0000
0x1000-0x1FFF RW RX memory Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
  • Address ending "00" - DRORC Message(47:32)
  • Address ending "01" - DRORC Message(31:16)
  • Address ending "10" - DRORC Message(15:0)
  • Address ending "11" - Receiving Channel number(7:0)
 0x0000
0x2000 R RX memory pointer(13:0) Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message. 0x0000
0x2001 R EventID FIFO count(3:0) Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. 0x0000
0x2002 R Current EventID(35:32) The EventID which is currently being matched. 0x0000
0x2003 R Current EventID(31:16) 0x0000
0x2004 R Current EventID(15:0) 0x0000
0x2005 R Newest EventID(35:32) The EventID most recently received from the Trigger system. 0x0000
0x2006 R Newest EventID(31:16) 0x0000
0x2007 R Newest EventID(15:0) 0x0000
0x2008 RW L0 Trigger Timeout(15:0) Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full. 0x000A
0x2009 RW Busy Condition(15:0) Status and control registers concerning the BUSY generation
  • Bit 15 - Busy because TTCrx_ready is low.
  • Bit 14 - Busy because MEB count >= MEB limit
  • Bit 13 - Busy because L0 timeout is active.
  • Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
  • Bit 11:8 - Unused
  • Bit 7:4 - Current MEB count.
  • Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
 0x0000
0x200A RW Halt FSM matching(0) If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs. 0x0001
0x200B T Force match(0) Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect. N/A
0x200C RW Re-Request Timeout(15:0) Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs. 0x07FF
0x200D R Current RequestID(3:0) Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. 0x0000
0x200E R Retry Count(15:0) Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID. 0x0000
0x2010 R Busy time(31:16) Holds value of counter for number of clock cycles BUSY has been asserted. 0x0000
0x2011 R Busy time(15:0) 0x0000
0x2012 RW RX mem filter(15:0) Allows filtering of messages that are stored in RX memory.
  • Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
  • Bit 15:8 allows enableing matching of individual bits 7-0.
 0x0000
0x2014 R Number of Channels Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time. N/A
0x2015 R Firmware Revision Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34 0x0022
0x2016 RW Stresstest Enable(0) Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available. 0x0000
0x21XX RW Channel Registers 'XX' in the address gives the channelnumber in hexadecimal.
  • Bit 0 is enable(1)/disable(0)
  • Bit 1 indicates that the current EventID has been matched on this channel.
 0x0001
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