Cadence Virtuoso overview

IC design flow using Cadence

We have access to several silicon technologies from different foundries

• 130nm CMOS process from Taiwan Semiconductor Manufacturing: TSMC 130nm process
• 130nm SiGe process from Innovations for High Performance Microelectronics: IHP 130nm process
• 350nm CMOS process from Austria Mikro Systeme: AMS 350nm process

Simulation

Virtuoso Testbench

Layout

Layout XL and IHP SG13S

Helpful stuff

MikroserverSetup - setup for easy connection to the mikroservers and Cadence Virtuoso

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.

ADEXL-butterfly-curves - Howto make DC butterfly curves easily.