Cadence Virtuoso overview

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Revision as of 12:20, 22 October 2014 by Oly002 (talk | contribs)

Analog IC design flow using Cadence from basics(Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)

TSMC 130nm process

AMS 350nm process


Helpful stuff

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.