Symbolsk løsning av nodeligninger med Matlab: Difference between revisions
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m Updated for newer Matalb versions (tested on R2020b) |
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% Kjetil Ullaland | % Kjetil Ullaland | ||
syms s Vin Vo Vgs Zc gm Rl Rs R | syms s C Vin Vo Vgs Zc gm Rl Rs R Av Avo | ||
eq1= | eq1=(Vo-Vgs)/(R+Zc)+gm*Vgs+Vo/Rl == 0; | ||
eq2= | eq2=(Vgs-Vo)/(R+Zc)+(Vgs-Vin)/Rs == 0; | ||
eq1=subs(eq1,Zc, | eq1=subs(eq1,Zc,1/(s*C)); | ||
eq2=subs(eq2,Zc, | eq2=subs(eq2,Zc,1/(s*C)); | ||
disp('KCL for circuit node 1:'); | disp('KCL for circuit node 1:'); | ||
pretty(eq1); | pretty(eq1); | ||
disp('KCL for circuit | disp('KCL for circuit node 2:'); | ||
pretty(eq2); | pretty(eq2); | ||
disp('Solve for | disp('Solve for Vo and Vin and calculate Av (Vo/Vin):'); | ||
solved=solve(eq1,eq2,Vo,Vin); | |||
pretty(simplify( | Av=solved.Vo/solved.Vin; | ||
pretty(simplify(Av)); | |||
pretty(subs(Av,Rl*gm,Avo)); | |||
</pre> | </pre> | ||
Revision as of 11:02, 23 September 2020
Using Kirchoff's current law (KCL) on a source follower configuration to find Vout as a function of Vin
% Using Kirchoff's current law (KCL) on a source follower configuration % to find Vo as a function of Vin % Only Cgd is considered (Zc) % Kjetil Ullaland syms s C Vin Vo Vgs Zc gm Rl Rs R Av Avo eq1=(Vo-Vgs)/(R+Zc)+gm*Vgs+Vo/Rl == 0; eq2=(Vgs-Vo)/(R+Zc)+(Vgs-Vin)/Rs == 0; eq1=subs(eq1,Zc,1/(s*C)); eq2=subs(eq2,Zc,1/(s*C)); disp('KCL for circuit node 1:'); pretty(eq1); disp('KCL for circuit node 2:'); pretty(eq2); disp('Solve for Vo and Vin and calculate Av (Vo/Vin):'); solved=solve(eq1,eq2,Vo,Vin); Av=solved.Vo/solved.Vin; pretty(simplify(Av)); pretty(subs(Av,Rl*gm,Avo));
Using Kirchoff's current law (KCL) on single transistor stage, fig. 9.18 to find Vo as a function of Is
% Using Kirchoff's current law (KCL) on single transistor stage, fig. 9.18 % to find Vo as a function of Is % Kjetil Ullaland, 2015 syms Vo V1 s gm R1 R2 C C1 C2 Is Zc Rz; %% With feedforward capacitor eq1=sym('(Vo-V1)/Zc+gm*V1+Vo/R2+Vo*s*C2=0'); eq2=sym('(V1-Vo)/Zc+V1*s*C1+V1/R1+Is=0'); eq1=subs(eq1,Zc,'1/(s*C)'); eq2=subs(eq2,Zc,'1/(s*C)'); solV1=solve(eq2,V1); eq3=subs(eq1,V1,solV1); SolVo=simplify(solve(eq3,[Vo])); disp('With capacitor only in feedforward loop'); pretty(simplify(SolVo/Is)); %% With series resistor and capacitor in feedforward loop eq1=sym('(Vo-V1)/(Zc+Rz)+gm*V1+Vo/R2+Vo*s*C2=0'); eq2=sym('(V1-Vo)/(Zc+Rz)+V1*s*C1+V1/R1+Is=0'); eq1=subs(eq1,Zc,'1/(s*C)'); eq2=subs(eq2,Zc,'1/(s*C)'); solV1=solve(eq2,V1); eq3=simplify(subs(eq1,V1,solV1)); SolVo=solve(eq3,[Vo]); disp('With series resistor and capacitor in feedforward loop'); pretty(simplify(SolVo/Is));