Revision as of 10:37, 18 October 2017

IC design flow using Cadence

We have access to several silicon technologies from different foundries

130nm CMOS process from Taiwan Semiconductor Manufacturing: TSMC 130nm process
130nm SiGe process from Innovations for High Performance Microelectronics: IHP 130nm process
350nm CMOS process from Austria Mikro Systeme: AMS 350nm process

MikroserverSetup - setup for easy connection to the mikroservers and Cadence Virtuoso

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.

ADEXL-butterfly-curves - Howto make DC butterfly curves easily.

@@ Line 1: / Line 1: @@
-=Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)=
+= IC design flow using Cadence =
-[[ TSMC 130nm process ]]
+We have access to several silicon technologies from different foundries
-[[ IHP 130nm process ]]
+* 130nm CMOS process from Taiwan Semiconductor Manufacturing: '''[[ TSMC 130nm process ]]'''
+* 130nm SiGe process from Innovations for High Performance Microelectronics: '''[[ IHP 130nm process ]]'''
-[[ AMS 350nm process ]]
+* 350nm  CMOS process from Austria Mikro Systeme: '''[[ AMS 350nm process ]]'''
 = Simulation =