Cadence Virtuoso overview: Difference between revisions
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[[Testbench|Virtuoso Testbench]] | [[Testbench|Virtuoso Testbench]] | ||
= Layout = | |||
[[Get schematic ready for layout]] | |||
[[Layout XL and IHP SG13S]] | |||
=Helpful stuff= | =Helpful stuff= | ||
Revision as of 08:06, 12 April 2016
Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)
Simulation
Layout
Get schematic ready for layout
Helpful stuff
Transistor operating point printer - Script to extract transistor operating point parameters after simulation.