Bitvis UVVM VHDL Verification Component Framework: Difference between revisions
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<pre> | |||
-- Copyright (c) 2016 by Bitvis AS. All rights reserved. | |||
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, | |||
-- contact Bitvis AS <support@bitvis.no>. | |||
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, | |||
-- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |||
-- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |||
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM. | |||
--======================================================================================================================== | |||
</pre> | |||
=== Introduction === | === Introduction === | ||
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verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the [http://bitvis.no/products/uvvm-vvc-framework/ Bitvis web page]. | verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the [http://bitvis.no/products/uvvm-vvc-framework/ Bitvis web page]. | ||
=== What's | === What's in the folders? === | ||
[[File: | [[File:1.png|thumb]] | ||
The download includes severals folders: | |||
* bitvis_irqc - example VHDL design + testbench | |||
* bitvis_uart - example VHDL design + testbench | |||
* bitvis_vip_sbi - Verification IP(VIP) for simple bus interface(SBI) | |||
* bitvis_vip_uart - VIP for UART TX and RX | |||
* uvvm_util - UVVM utility library - sufficient for simple testbenches | |||
* uvvm_vvc_framework - Framework for more advanced tutorials | |||
=== Let's create our own testbench for the IRQC === | |||
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. Open up bitvis_irqc/tb/irqc_tb.vhd and delete it! Let's start over.... | |||
<pre> | |||
-- Add the standard libraries | |||
library IEEE; | |||
use IEEE.std_logic_1164.all; | |||
use IEEE.numeric_std.all; | |||
library STD; | |||
use std.env.all; | |||
--Also add the Bitvis UVVM Utility Library | |||
library uvvm_util; | |||
context uvvm_util.uvvm_util_context; | |||
--And the Verification IP for the simple bus interface | |||
library bitvis_vip_sbi; | |||
use bitvis_vip_sbi.sbi_bfm_pkg.all; | |||
--And the design's package file | |||
use work.irqc_pif_pkg.all; | |||
</pre> | |||
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. We can start trying out the example testbench before continuing. Open up Questa/Modelsim. | |||
Change directory to the script folder (obviously change to your folder.....): | |||
<pre> | |||
cd ~/phys321/bitviswiki/bitvis_irqc/script | |||
do compile_and_sim_all.do | |||
</pre> |
Revision as of 14:04, 26 January 2016
-- Copyright (c) 2016 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <support@bitvis.no>. -- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -- INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -- IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM. --========================================================================================================================
Introduction
Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the Bitvis web page.
What's in the folders?
The download includes severals folders:
- bitvis_irqc - example VHDL design + testbench
- bitvis_uart - example VHDL design + testbench
- bitvis_vip_sbi - Verification IP(VIP) for simple bus interface(SBI)
- bitvis_vip_uart - VIP for UART TX and RX
- uvvm_util - UVVM utility library - sufficient for simple testbenches
- uvvm_vvc_framework - Framework for more advanced tutorials
Let's create our own testbench for the IRQC
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. Open up bitvis_irqc/tb/irqc_tb.vhd and delete it! Let's start over....
-- Add the standard libraries library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library STD; use std.env.all; --Also add the Bitvis UVVM Utility Library library uvvm_util; context uvvm_util.uvvm_util_context; --And the Verification IP for the simple bus interface library bitvis_vip_sbi; use bitvis_vip_sbi.sbi_bfm_pkg.all; --And the design's package file use work.irqc_pif_pkg.all;
Copy the bitvis_irqc, bitvis_vip_sbi and uvvm_util to another location before editing the files. We can start trying out the example testbench before continuing. Open up Questa/Modelsim. Change directory to the script folder (obviously change to your folder.....):
cd ~/phys321/bitviswiki/bitvis_irqc/script do compile_and_sim_all.do