Cadence Virtuoso overview: Difference between revisions
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[[ AMS 350nm process ]] | [[ AMS 350nm process ]] | ||
= Simulation = | |||
[[Testbench|Virtuoso Testbench]] | |||
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Revision as of 09:24, 27 October 2015
Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)
Simulation
Helpful stuff
Transistor operating point printer - Script to extract transistor operating point parameters after simulation.