SAMPA/SAMPA DAQ Registers

SAMPA DAQ Registers

Command and Control module registers

The registers for the command and control module, located at address 0x0000 from the UART or 0xFF200000 from the HPS, is listed in table 4.1

Register name		Address	Type	Default		Description
SC_ADD	[15:0]	0x00	RW	0x00	[4:0]	Slow control: Register address
			RW	0x00	[9:5]	Slow control: Channel address
			RW	0x00	[13:10]	Slow control: Chip address
			RW	0x00	[14]	Slow control: Broadcast
			RW	0x00	[15]	Slow control: Write/ not read
SC_DAT	[19:0]	0x01	RW	0x00	[19:0]	Slow control: Data to write
SC_MASK	[19:0]	0x02	RW	0x00	[19:0]	Slow control: Mask for writing *
CMD	[31:0]	0x03	RW	0x00	[15:0]	Commands, see table 4.2
			RW	0x00	[31:15]	Loop count for commands
SC_RLT	[19:0]	0x04	R	0x00	[12:0]	Slow control: Response from SAMPA
SC_ERR	[1:0]	0x05	R	0x00	[0]	Error: Timeout waiting for response from slow control
			R	0x00	[1]	Error: Response from SAMPA not as expected
LNK_STS	[31:0]	0x06	R	0x00	[31:0]	Ethernet link status *
EVT_CFG	[31:0]	0x07	RW	0x01	[1:0]	Test signal output, see table 4.3
			RW	0x00	[2]	Enable SLVS testing
			RW	0x00	[3]	Enable continuous readout of shiftregister
			RW	0x00	[31:3]	Reserved *
EVT_CNT	[31:0]	0x08	R	0x00	[31:0]	Reserved *
EV_BL	[31:0]	0x09	R	0x00	[31:0]	Reserved *
SMP_STS1	[30:0]	0x0A	R			Status of signals to and from SAMPA (updated every clock cycle)
			R		[12:0]	Test data output from SAMPA
			R		[16:13]	Serial out [3:0]
			R		[18:17]	Number of serial out
			R		[19]	Enable ZSU
			R		[20]	Enable BC2
			R		[21]	Enable TCFU (deprecated)
			R		[22]	Enable BC1
			R		[25:23]	Select test output
			R		[26]	Select ADC0 or test input
			R		[30:27]	Chip address
SMP_STS2	[5:0]	0x0B	R			Status of signals to and from SAMPA cont.
			R		[0]	Slow control to SAMPA
			R		[1]	Slow control from SAMPA
			R		[2]	Reset_n
			R		[3]	Event trigger
			R		[4]	Heartbeat trigger
			R		[5]	Sync signal
SMP_CFG	[13:0]	0x0C	RW			SAMPA static signals, see SAMPA spec document for further details
			RW	0x02	[1:0]	Number of serial out
			RW	0x00	[2]	Enable ZSU
			RW	0x00	[3]	Enable BC2
			RW	0x01	[4]	Enable TCFU
			RW	0x01	[5]	Enable BC1
			RW	0x03	[8:6]	Select test output
			RW	0x01	[9]	Select ADC0 or test input
			RW	0x01	[13:10]	Chip address
SLVS_ERR	[15:0]	0x0D	R	0x00		SLVS errors detected
RAD_ERR	[31:0]	0x0E	R			Errors detected in shiftregister test
			R	0x00	[15:0]	Bit 0 errors
			R	0x00	[31:16]	Bit 1 errors
VER	[31:0]	0x0F	R			SVN version build was based on in dec

Commands for command and control unit.

Value	Description
0x1	Reset FPGA and SAMPA
0x2	Reset SAMPA
0x3	Send event trigger
0x4	Send heartbeat trigger
0x5	Send sync signal
0x6	Run readout of shiftregister once (RAD)
0x7	Reset errors in shiftregister count (RAD_ERR)
0x8	Execute slow control command
0x9	Reset HPS

Test signals available for generation.

Value	Description
0x0	Constant zeros
0x1	Sine wave, full wave, 512 samples pulse width
0x2	Saw wave, full wave, 512 samples pulse width
0x3	Triangle wave, full wave, 1024 samples pulse width

Data manager registers

The registers for the data manager module, located at address 0x0040 from the UART or 0xFF201000 from the HPS, is listed in table 4.4.

Register name		Address	Type	Default		Description
CNTRL	[7:0]	0x00	RW	0x00		Control register
			RW	0x00	[0]	Enable acquisition
			RW	0x00	[7:1]	Reserved
PKT0	[31:0]	0x01	R	0x00	[31:0]	Packets written to memory from channel 0
PKT1	[31:0]	0x02	R	0x00	[31:0]	Packets written to memory from channel 1
PKT2	[31:0]	0x03	R	0x00	[31:0]	Packets written to memory from channel 2
PKT3	[31:0]	0x04	R	0x00	[31:0]	Packets written to memory from test-input/ADC
FIFO0	[8:0]	0x05	R	0x00	[8:0]	Number of 64 bit words in FIFO 0
FIFO1	[8:0]	0x05	R	0x00	[8:0]	Number of 64 bit words in FIFO 1
FIFO2	[8:0]	0x05	R	0x00	[8:0]	Number of 64 bit words in FIFO 2
FIFO3	[8:0]	0x05	R	0x00	[8:0]	Number of 64 bit words in FIFO 3