Busy Box and related/BusyBox Registers

Busy Box Status and Contol Registers
Name	Address	Mode	Description	Default Value
TX module(15:0)	0x0001	RW	For sending messages to DRORCs. Bit 7:0 is TX data. Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.	0x0000
RX memory	0x1000-0x1FFF	RW	Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses: Address ending "00" - DRORC Message(47:32) Address ending "01" - DRORC Message(31:16) Address ending "10" - DRORC Message(15:0) Address ending "11" - Receiving Channel number(7:0)	0x0000
RX memory pointer(13:0)	0x2000	R	Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.	0x0000
EventID FIFO count(3:0)	0x2001	R	Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.	0x0000
Current EventID(35:32)	0x2002	R	The EventID which is currently being matched.	0x0000
Current EventID(31:16)	0x2003	R		0x0000
Current EventID(15:0)	0x2004	R		0x0000
Newest EventID(35:32)	0x2005	R	The EventID most recently received from the Trigger system.	0x0000
Newest EventID(31:16)	0x2006	R		0x0000
Newest EventID(15:0)	0x2007	R		0x0000
L0 Trigger Timeout(15:0)	0x2008	RW	Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.	0x000A
Busy Condition(15:0)	0x2009	RW	Status and control registers concerning the BUSY generation Bit 15 - Busy because TTCrx_ready is low. Bit 14 - Busy because MEB count >= MEB limit Bit 13 - Busy because L0 timeout is active. Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence. Bit 11:8 - Unused Bit 7:4 - Current MEB count. Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.	0x0000
Halt FSM matching(0)	0x200A	RW	If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.	0x0001
Force match(0)	0x200B	T	Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.	N/A
Re-Request Timeout(15:0)	0x200C	RW	Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.	0x07FF
Current RequestID(3:0)	0x200D	R	Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.	0x0000
Retry Count(15:0)	0x200E	R	Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.	0x0000
Busy time(31:16)	0x2010	R	Holds value of counter for number of clock cycles BUSY has been asserted.	0x0000
Busy time(15:0)	0x2011	R		0x0000
RX mem filter(15:0)	0x2012	RW	Allows filtering of messages that are stored in RX memory. Bit 7:0 is the pattern that will be matched with the channelnumber of the message. Bit 15:8 allows enableing matching of individual bits 7-0.	0x0000
Number of Channels	0x2014	R	Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.	N/A
Firmware Revision	0x2015	R	Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34	0x0022
Stresstest Enable(0)	0x2016	RW	Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.	0x0000
Channel Registers	0x21XX	RW	'XX' in the address gives the channelnumber in hexadecimal. Bit 0 is enable(1)/disable(0) Bit 1 indicates that the current EventID has been matched on this channel.	0x0001

Trigger Receiver Module Status and Control Registers
Name	Address	Mode	Bit slice	Description
Control	0x3000	RW	[15:13]	Unused
		RW	[12]	Trigger Input Mask Enable. Default=0
		RW	[11]	L1a message mask. Default=1
		RW	[10]	L2 Timeout FIFO storage mask. Default=1
		RW	[9]	L2r FIFO storage mask. Default=1
		RW	[8]	L2a FIFO storage mask. Default=1
		RW	[7:4]	Unused
		RW	[3]	L0 support. Default=1
		RW	[2]	Enable RoI decoding. Default=0
		RW	[1]	Disable_error_masking. Default=0
		RW	[0]	Serial B channel on/off. Default=1
Control	0x3001	R	[15:8]	Trigger Receiver Version. Default=0x13
		R	[7:4]	CDH version. Default=0x2
		R	[3]	Not Used
		R	[2]	Busy (receiving sequence) -
		R	[1]	Run Active -
		R	[0]	Bunch_counter overflow -
Module Reset	0x3002	T	N/A	Reset Module
Reset Counters	0x3008	T	N/A	Write to this registers will reset the counters in the module
Issue Testmode	0x300A	T	N/A	Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
L1_Latency	0x300C	RW	[15:12]	Uncertainty region +- N. default value 0x2 (50 ns)
		RW	[11:0]	Latency from L0 to L1. default value 0x0D4 (5.3 us)
L2_Latency MAX	0x300E	RW	[15:0]	Max Latency from BC0 to L2. default value 0x4E20 (500 us)
L2_Latency MIN	0x300F	RW	[15:0]	Min Latency from BC0 to L2. default value 0x0C80 (80 us)
L1_msg_latency MAX	0x3012	RW	[15:0]	Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
L1_msg_latency MIN	0x3013	RW	[15:0]	Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
Pre_pulse_counter	0x3016	R	[15:0]	Number of decoded pre-pulses.
BCID_Local	0x3018	R	[11:0]	Number of bunchcrossings at arrival of L1 trigger.
L0_counter	0x301A	R	[15:0]	Number of L0 triggers
L1_counter	0x301C	R	[15:0]	Number of L1 triggers
L1_msg_counter	0x301E	R	[15:0]	Number of successfully decoded L1 messages
L2a_counter	0x3020	R	[15:0]	Number of successfully decoded L2a messages
L2r_counter	0x3022	R	[15:0]	Number of successfully decoded L2r messages
Bunchcounter	0x3026	R	[11:0]	Debug: Number of bunchcrossings
SingleHammingErrorCnt	0x302C	R	[15:0]	Number of single bit hamming errors
DoubleHammingErrorCnt	0x302D	R	[15:0]	Number of double bit hamming errors
MsgDecodingErrorCnt	0x302E	R	[15:0]	Number of message decoding errors
SeqTimoutErrorCnt	0x302F	R	[15:0]	Number of errors related to sequence and timeouts.
Buffered_events	0x3040	R	[4:0]	Number of events stored in the FIFO.
DAQ_Header01	0x3042	R	[15:0]	Latest received DAQ Header 1 [15:0]
DAQ_Header01	0x3043	R	[15:0]	Latest received DAQ Header 1 [31:16]
DAQ_Header02	0x3044	R	[15:0]	Latest received DAQ Header 2 [15:0]
DAQ_Header02	0x3045	R	[15:0]	Latest received DAQ Header 2 [31:16]
DAQ_Header03	0x3046	R	[15:0]	Latest received DAQ Header 3 [15:0]
DAQ_Header03	0x3047	R	[15:0]	Latest received DAQ Header 3 [31:16]
DAQ_Header04	0x3048	R	[15:0]	Latest received DAQ Header 4 [15:0]
DAQ_Header04	0x3049	R	[15:0]	Latest received DAQ Header 4 [31:16]
DAQ_Header05	0x304a	R	[15:0]	Latest received DAQ Header 5 [15:0]
DAQ_Header05	0x304b	R	[15:0]	Latest received DAQ Header 5 [31:16]
DAQ_Header06	0x304c	R	[15:0]	Latest received DAQ Header 6 [15:0]
DAQ_Header06	0x304d	R	[15:0]	Latest received DAQ Header 6 [31:16]
DAQ_Header07	0x304e	R	[15:0]	Latest received DAQ Header 7 [15:0]
DAQ_Header07	0x304f	R	[15:0]	Latest received DAQ Header 7 [31:16]
Event_info	0x4051	R	[12:0]	Latest Received Event information:
		R	[12]	Include payload
		R	[11]	Event has L2 Accept trigger
		R	[10]	Event has L2 Reject trigger
		R	[9]	Calibration trigger event
		R	[8]	Software trigger event
		R	[4:7]	Calibration/SW trigger type (= RoC)
		R	[3]	NA(=‘0’)
		R	[2]	NA(=‘0’)
		R	[1]	Region of Interest announced (=ESR)
		R	[0]	NA(=’0’)
Event_error	0x4053	R	[15:0]	Latest Received Event error conditions:
		R	[15]	L1 message arrives outside legal timeslot
		R	[14]	Missing L1
		R	[13]	Boundary L1
		R	[12]	Spurious L1
		R	[11]	Missing L0
		R	[10]	Spurious L0
		R	[9]	TTCrx Address Error (not X”0003”)
		R	[8]	NA (= ‘0’)
		R	[7]	Incomplete L2a Message
		R	[6]	Incomplete L1 Message
		R	[5]	Unknown Message Address Received
		R	[4]	Double Bit Hamming Error Broadcast.
		R	[3]	Single Bit Hamming Error Broadcast.
		R	[2]	Double Bit Hamming Error Individually Addr.
		R	[1]	Single Bit Hamming Error Individually Addr.
		R	[0]	Serial B Stop Bit Error
Event_error	0x4054	R	[8:0]	Latest Received Event error conditions:
		R	[8]	NA (= ‘0’)
		R	[7]	L2 message content error
		R	[6]	L1 message content error
		R	[5]	Prepulse error (=0; possible future use)
		R	[4]	NA (= ‘0’)
		R	[3]	NA (= ‘0’)
		R	[2]	L2 message missing/timeout
		R	[1]	L2 message arrives outside legal timeslot
		R	[0]	L1 message missing/timeout