Busy Box and related/BusyBox Registers: Difference between revisions
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====Busy Box Status and Contol Registers==== | ====Busy Box Status and Contol Registers==== | ||
| Line 10: | Line 11: | ||
|0x0001 | |0x0001 | ||
|RW | |RW | ||
|TX module | |TX module(15:0) | ||
|For sending messages to DRORCs. | |For sending messages to DRORCs. | ||
* Bit 7 | * Bit 7:0 is TX data. | ||
* Bit 15 | * Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels. | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
| | |0x1000-0x1FFF | ||
|RW | |RW | ||
|RX memory | |RX memory | ||
|Memory where all messages received from DRORCs will be stored. | |Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses: | ||
* Address ending "00" - DRORC Message(47:32) | |||
* Address ending "01" - DRORC Message(31:16) | |||
* Address ending "10" - DRORC Message(15:0) | |||
* Address ending "11" - Receiving Channel number(7:0) | |||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2000 | |0x2000 | ||
|R | |R | ||
|RX memory pointer | |RX memory pointer(13:0) | ||
|Holds the value where the next message will be written in RX memory. | |Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message. | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2001 | |0x2001 | ||
|R | |R | ||
|EventID FIFO count | |EventID FIFO count(3:0) | ||
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. | |Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. | ||
|0x0000 | |0x0000 | ||
| Line 36: | Line 41: | ||
|0x2002 | |0x2002 | ||
|R | |R | ||
|Current EventID(35 | |Current EventID(35:32) | ||
|rowspan="3"|The EventID which is currently being matched. | |rowspan="3"|The EventID which is currently being matched. | ||
|0x0000 | |0x0000 | ||
| Line 42: | Line 47: | ||
|0x2003 | |0x2003 | ||
|R | |R | ||
|Current EventID(31 | |Current EventID(31:16) | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2004 | |0x2004 | ||
|R | |R | ||
|Current EventID(15 | |Current EventID(15:0) | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2005 | |0x2005 | ||
|R | |R | ||
|Newest EventID(35 | |Newest EventID(35:32) | ||
|rowspan="3"|The EventID most recently received from the Trigger system. | |rowspan="3"|The EventID most recently received from the Trigger system. | ||
|0x0000 | |0x0000 | ||
| Line 58: | Line 63: | ||
|0x2006 | |0x2006 | ||
|R | |R | ||
|Newest EventID(31 | |Newest EventID(31:16) | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2007 | |0x2007 | ||
|R | |R | ||
|Newest EventID(15 | |Newest EventID(15:0) | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2008 | |0x2008 | ||
|RW | |RW | ||
|L0 Trigger Timeout | |L0 Trigger Timeout(15:0) | ||
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full. | |Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full. | ||
|0x000A | |0x000A | ||
| Line 74: | Line 79: | ||
|0x2009 | |0x2009 | ||
|RW | |RW | ||
|Busy Condition | |Busy Condition(15:0) | ||
|Status and control registers concerning the BUSY generation | |Status and control registers concerning the BUSY generation | ||
* Bit 15 - Busy because TTCrx_ready is low. | * Bit 15 - Busy because TTCrx_ready is low. | ||
| Line 80: | Line 85: | ||
* Bit 13 - Busy because L0 timeout is active. | * Bit 13 - Busy because L0 timeout is active. | ||
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence. | * Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence. | ||
* Bit 7 | * Bit 11:8 - Unused | ||
* Bit 3 | * Bit 7:4 - Current MEB count. | ||
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted. | |||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x200A | |0x200A | ||
|RW | |RW | ||
|Halt FSM matching | |Halt FSM matching(0) | ||
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs. | |If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs. | ||
|0x0001 | |0x0001 | ||
|- | |- | ||
|0x200B | |0x200B | ||
|T | |T | ||
|Force match | |Force match(0) | ||
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect. | |Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect. | ||
|N/A | |N/A | ||
| Line 98: | Line 104: | ||
|0x200C | |0x200C | ||
|RW | |RW | ||
|Re-Request Timeout | |Re-Request Timeout(15:0) | ||
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs. | |Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs. | ||
|0x07FF | |0x07FF | ||
| Line 104: | Line 110: | ||
|0x200D | |0x200D | ||
|R | |R | ||
|Current RequestID | |Current RequestID(3:0) | ||
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. | |Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. | ||
|0x0000 | |0x0000 | ||
| Line 110: | Line 116: | ||
|0x200E | |0x200E | ||
|R | |R | ||
|Retry Count(15 | |Retry Count(15:0) | ||
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID. | |Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID. | ||
|0x0000 | |0x0000 | ||
| Line 116: | Line 122: | ||
|0x2010 | |0x2010 | ||
|R | |R | ||
|Busy time(31 | |Busy time(31:16) | ||
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted. | |rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted. | ||
|0x0000 | |0x0000 | ||
| Line 122: | Line 128: | ||
|0x2011 | |0x2011 | ||
|R | |R | ||
|Busy time(15 | |Busy time(15:0) | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
|0x2012 | |0x2012 | ||
|RW | |RW | ||
|RX mem filter | |RX mem filter(15:0) | ||
|Allows filtering of messages that are stored in RX memory. | |Allows filtering of messages that are stored in RX memory. | ||
*Bit 7 | *Bit 7:0 is the pattern that will be matched with the channelnumber of the message. | ||
*Bit 15 | *Bit 15:8 allows enableing matching of individual bits 7-0. | ||
|0x0000 | |0x0000 | ||
|- | |||
|0x2014 | |||
|R | |||
|Number of Channels | |||
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time. | |||
|N/A | |||
|- | |- | ||
|0x2015 | |0x2015 | ||
| Line 148: | Line 160: | ||
|RW | |RW | ||
|Channel Registers | |Channel Registers | ||
|'XX' in the address gives the channelnumber in hexadecimal. | |'XX' in the address gives the channelnumber in hexadecimal. | ||
*Bit 0 is enable(1)/disable(0) | *Bit 0 is enable(1)/disable(0) | ||
*Bit 1 indicates that the current EventID has been matched on this channel. | *Bit 1 indicates that the current EventID has been matched on this channel. | ||
|0x0001 | |0x0001 | ||
|} | |} | ||
Revision as of 09:06, 21 October 2009
Busy Box Status and Contol Registers
| Address | Mode | Name | Description | Default Value |
|---|---|---|---|---|
| 0x0001 | RW | TX module(15:0) | For sending messages to DRORCs.
|
0x0000 |
| 0x1000-0x1FFF | RW | RX memory | Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
|
0x0000 |
| 0x2000 | R | RX memory pointer(13:0) | Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message. | 0x0000 |
| 0x2001 | R | EventID FIFO count(3:0) | Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. | 0x0000 |
| 0x2002 | R | Current EventID(35:32) | The EventID which is currently being matched. | 0x0000 |
| 0x2003 | R | Current EventID(31:16) | 0x0000 | |
| 0x2004 | R | Current EventID(15:0) | 0x0000 | |
| 0x2005 | R | Newest EventID(35:32) | The EventID most recently received from the Trigger system. | 0x0000 |
| 0x2006 | R | Newest EventID(31:16) | 0x0000 | |
| 0x2007 | R | Newest EventID(15:0) | 0x0000 | |
| 0x2008 | RW | L0 Trigger Timeout(15:0) | Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full. | 0x000A |
| 0x2009 | RW | Busy Condition(15:0) | Status and control registers concerning the BUSY generation
|
0x0000 |
| 0x200A | RW | Halt FSM matching(0) | If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs. | 0x0001 |
| 0x200B | T | Force match(0) | Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect. | N/A |
| 0x200C | RW | Re-Request Timeout(15:0) | Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs. | 0x07FF |
| 0x200D | R | Current RequestID(3:0) | Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. | 0x0000 |
| 0x200E | R | Retry Count(15:0) | Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID. | 0x0000 |
| 0x2010 | R | Busy time(31:16) | Holds value of counter for number of clock cycles BUSY has been asserted. | 0x0000 |
| 0x2011 | R | Busy time(15:0) | 0x0000 | |
| 0x2012 | RW | RX mem filter(15:0) | Allows filtering of messages that are stored in RX memory.
|
0x0000 |
| 0x2014 | R | Number of Channels | Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time. | N/A |
| 0x2015 | R | Firmware Revision | Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34 | 0x0022 |
| 0x2016 | RW | Stresstest Enable(0) | Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available. | 0x0000 |
| 0x21XX | RW | Channel Registers | 'XX' in the address gives the channelnumber in hexadecimal.
|
0x0001 |
