Busy Box and related/BusyBox Registers: Difference between revisions
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{|border="1" cellpadding="5" cellspacing="0" | {|border="1" cellpadding="5" cellspacing="0" | ||
!colspan="5"| Busy Box Status and | !colspan="5"| Busy Box Status and Control Registers | ||
|- | |- | ||
!width="170"|Name | !width="170"|Name | ||
Line 20: | Line 20: | ||
|RW | |RW | ||
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses: | |Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses: | ||
* Address ending "00" - | * Address ending "00" - 0x0 & RequestID(3:0) & OrbitID(23:16) | ||
* Address ending "01" - | * Address ending "01" - OrbitID(15:0) | ||
* Address ending "10" - | * Address ending "10" - 0x0 BunchCountID(11:0) | ||
* Address ending "11" - | * Address ending "11" - DRORCID(7:0) & ChannelNumber(7:0) | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
Line 70: | Line 70: | ||
|0x0000 | |0x0000 | ||
|- | |- | ||
| | |L1 Trigger Timeout(15:0) | ||
|0x2008 | |0x2008 | ||
|RW | |RW | ||
|Time in 10 us resolution the 'busy' will be asserted after an | |Time in 10 us resolution the 'busy' will be asserted after an L1A trigger. Note: The busy will not be deasserted if the buffers are full. | ||
|0x000A | |0x000A | ||
|- | |- | ||
Line 82: | Line 82: | ||
* Bit 15 - Busy because TTCrx_ready is low. | * Bit 15 - Busy because TTCrx_ready is low. | ||
* Bit 14 - Busy because MEB count >= MEB limit | * Bit 14 - Busy because MEB count >= MEB limit | ||
* Bit 13 - Busy because | * Bit 13 - Busy because L1 timeout is active. | ||
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence. | * Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence. | ||
* Bit 11:8 - Unused | * Bit 11 - Busy because the maximum Trigger Burst length has been exceeded. | ||
* Bit 10 - Busy because two buffers are, or have been used, in new sparse mode | |||
* Bit 9:8 - Unused | |||
* Bit 7:4 - Current MEB count. | * Bit 7:4 - Current MEB count. | ||
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted. | * Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted. | ||
Line 147: | Line 149: | ||
|0x2015 | |0x2015 | ||
|R | |R | ||
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : | |Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 54 | ||
| | |0x0036 | ||
|- | |- | ||
|Stresstest Enable(0) | |Stresstest Enable(0) | ||
Line 154: | Line 156: | ||
|RW | |RW | ||
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available. | |Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available. | ||
|0x0000 | |||
|- | |||
|Burst Size(5:0) | |||
|0x2017 | |||
|RW | |||
|The maximum burst size. A value of 0 disables the Burst Interlock feature. Maximum value is 63. | |||
|0x0000 | |||
|- | |||
|Burst Interlock Leak Time(15:0) | |||
|0x2018 | |||
|RW | |||
|Leak time for the Burst Interlock "leaky bucket" defined in steps of 10 us. Maximum leak time is 655.4 ms. | |||
|0x0000 | |||
|- | |||
|Trigger Mode(2:0) | |||
|0x2019 | |||
|RW | |||
|Control registers concerning the BUSY/trigger mode | |||
* Bit 2 - Not used | |||
* Bit 1 - New sparse mode enabled | |||
* Bit 0 - Not used | |||
|0x0000 | |||
|- | |||
|Current Trigger Event Info(12:0) | |||
|0x2050 | |||
|R | |||
|Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping. | |||
|0x0000 | |||
|- | |||
|Current Trigger Event Error(24:16) | |||
|0x2051 | |||
|R | |||
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping. | |||
|0x0000 | |||
|- | |||
|Current Trigger Event Error(15:0) | |||
|0x2052 | |||
|R | |||
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping. | |||
|0x0000 | |||
|- | |||
|Newest Trigger Event Info(12:0) | |||
|0x2054 | |||
|R | |||
|Holds the Event Info for newest eventID as reported by the TRM. See TRM registers for bitmapping. | |||
|0x0000 | |||
|- | |||
|Newest Trigger Event Error(24:16) | |||
|0x2055 | |||
|R | |||
|Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping. | |||
|0x0000 | |||
|- | |||
|Newest Trigger Event Error(15:0) | |||
|0x2056 | |||
|R | |||
|Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping. | |||
|0x0000 | |0x0000 | ||
|- | |- | ||
Line 165: | Line 224: | ||
|- | |- | ||
|} | |} | ||
{|border="1" cellpadding="5" cellspacing="0" | {|border="1" cellpadding="5" cellspacing="0" | ||
Line 172: | Line 232: | ||
!Address | !Address | ||
!Mode | !Mode | ||
!width=" | !width="90"|Bit slice | ||
!Description | !Description | ||
|---- | |---- | ||
|Control | |rowspan="11"|Control | ||
|0x3000 | |rowspan="11"|0x3000 | ||
|RW | |RW | ||
|[15:13] | |[15:13] | ||
|Unused | |Unused | ||
|---- | |---- | ||
| | |RW | ||
|[12] | |[12] | ||
|Trigger Input Mask Enable. Default=0 | |Trigger Input Mask Enable. Default=0 | ||
|---- | |---- | ||
| | |RW | ||
|[11] | |[11] | ||
|L1a message mask. Default=1 | |L1a message mask. Default=1 | ||
|---- | |---- | ||
| | |RW | ||
|[10] | |[10] | ||
|L2 Timeout FIFO storage mask. Default=1 | |L2 Timeout FIFO storage mask. Default=1 | ||
|---- | |---- | ||
| | |RW | ||
|[9] | |[9] | ||
|L2r FIFO storage mask. Default=1 | |L2r FIFO storage mask. Default=1 | ||
|---- | |---- | ||
| | |RW | ||
|[8] | |[8] | ||
|L2a FIFO storage mask. Default=1 | |L2a FIFO storage mask. Default=1 | ||
|---- | |---- | ||
| | |RW | ||
|[7:4] | |[7:4] | ||
|Unused | |Unused | ||
|---- | |---- | ||
| | |RW | ||
|[3] | |[3] | ||
|L0 support. Default=1 | |L0 support. Default=1 | ||
|---- | |---- | ||
| | |RW | ||
|[2] | |[2] | ||
| | |Unused | ||
|---- | |---- | ||
| | |RW | ||
|[1] | |[1] | ||
|Disable_error_masking. Default=0 | |Disable_error_masking. Default=0 | ||
|---- | |---- | ||
| | |RW | ||
|[0] | |[0] | ||
|Serial B channel on/off. Default=1 | |Serial B channel on/off. Default=1 | ||
|---- | |---- | ||
|Control | |rowspan="6"|Control | ||
|0x3001 | |rowspan="6"|0x3001 | ||
| | |R | ||
|[15:8] | |[15:8] | ||
|Trigger Receiver Version. Default= | |Trigger Receiver Version. Default=0x16 | ||
|---- | |---- | ||
| | |R | ||
|[7:4] | |[7:4] | ||
|CDH version. Default=0x2 | |CDH version. Default=0x2 | ||
|---- | |---- | ||
| | |R | ||
|[3] | |[3] | ||
|Not | |Not used | ||
|---- | |---- | ||
| | |R | ||
|[2] | |[2] | ||
|Busy (receiving sequence) - | |Busy (receiving sequence) - | ||
|---- | |---- | ||
| | |R | ||
|[1] | |[1] | ||
|Run Active - | |Run Active - | ||
|---- | |---- | ||
| | |R | ||
|[0] | |[0] | ||
|Bunch_counter overflow - | |Bunch_counter overflow - | ||
Line 295: | Line 325: | ||
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature. | |Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature. | ||
|---- | |---- | ||
|L1_Latency | |rowspan="2"|L1_Latency | ||
|0x300C | |rowspan="2"|0x300C | ||
|RW | |RW | ||
|[15:12] | |[15:12] | ||
|Uncertainty region +- N. default value 0x2 (50 ns) | |Uncertainty region +- N. default value 0x2 (50 ns) | ||
|---- | |---- | ||
|RW | |RW | ||
|[11:0] | |[11:0] | ||
Line 319: | Line 347: | ||
|Min Latency from BC0 to L2. default value 0x0C80 (80 us) | |Min Latency from BC0 to L2. default value 0x0C80 (80 us) | ||
|---- | |---- | ||
|L1_msg_latency MAX | |L1_msg_latency MAX | ||
| | |0x3014 | ||
|RW | |RW | ||
|[15:0] | |[15:0] | ||
Line 326: | Line 356: | ||
|---- | |---- | ||
|L1_msg_latency MIN | |L1_msg_latency MIN | ||
| | |0x3015 | ||
|RW | |RW | ||
|[15:0] | |[15:0] | ||
Line 493: | Line 523: | ||
|Latest received DAQ Header 7 [31:16] | |Latest received DAQ Header 7 [31:16] | ||
|---- | |---- | ||
|Event_info | |Event_info | ||
| | |0x3050 | ||
|R | |R | ||
|[12:0] | |[12:0] | ||
|Latest Received Event information: | |Latest Received Event information: | ||
|---- | |---- | ||
| | |colspan="2" rowspan="10"| | ||
| | |||
|R | |R | ||
|[12] | |[12] | ||
|Include payload | |Include payload | ||
|---- | |---- | ||
|R | |R | ||
|[11] | |[11] | ||
|Event has L2 Accept trigger | |Event has L2 Accept trigger | ||
|---- | |---- | ||
|R | |R | ||
|[10] | |[10] | ||
|Event has L2 Reject trigger | |Event has L2 Reject trigger | ||
|---- | |---- | ||
|R | |R | ||
|[9] | |[9] | ||
|Calibration trigger event | |Calibration trigger event | ||
|---- | |---- | ||
|R | |R | ||
|[8] | |[8] | ||
|Software trigger event | |Software trigger event | ||
|---- | |---- | ||
|R | |R | ||
|[4:7] | |[4:7] | ||
|Calibration/SW trigger type (= RoC) | |Calibration/SW trigger type (= RoC) | ||
|---- | |---- | ||
|R | |R | ||
|[3] | |[3] | ||
|NA(=‘0’) | |NA(=‘0’) | ||
|---- | |---- | ||
|R | |R | ||
|[2] | |[2] | ||
|NA(=‘0’) | |NA(=‘0’) | ||
|---- | |---- | ||
|R | |R | ||
|[1] | |[1] | ||
|Region of Interest announced (=ESR) | |Region of Interest announced (=ESR) | ||
|---- | |---- | ||
|R | |R | ||
|[0] | |[0] | ||
Line 560: | Line 571: | ||
|---- | |---- | ||
|Event_error | |Event_error | ||
| | |0x3052 | ||
|R | |R | ||
|[15:0] | |[15:0] | ||
|Latest Received Event error conditions: | |Latest Received Event error conditions: | ||
|---- | |---- | ||
| | |colspan="2" rowspan="16"| | ||
| | |||
|R | |R | ||
|[15] | |[15] | ||
|L1 message arrives outside legal timeslot | |L1 message arrives outside legal timeslot | ||
|---- | |---- | ||
|R | |R | ||
|[14] | |[14] | ||
|Missing L1 | |Missing L1 | ||
|---- | |---- | ||
|R | |R | ||
|[13] | |[13] | ||
|Boundary L1 | |Boundary L1 | ||
|---- | |---- | ||
|R | |R | ||
|[12] | |[12] | ||
|Spurious L1 | |Spurious L1 | ||
|---- | |---- | ||
|R | |R | ||
|[11] | |[11] | ||
|Missing L0 | |Missing L0 | ||
|---- | |---- | ||
|R | |R | ||
|[10] | |[10] | ||
|Spurious L0 | |Spurious L0 | ||
|---- | |---- | ||
|R | |R | ||
|[9] | |[9] | ||
|TTCrx Address Error (not X”0003”) | |TTCrx Address Error (not X”0003”) | ||
|---- | |---- | ||
|R | |R | ||
|[8] | |[8] | ||
|NA (= ‘0’) | |NA (= ‘0’) | ||
|---- | |---- | ||
|R | |R | ||
|[7] | |[7] | ||
|Incomplete L2a Message | |Incomplete L2a Message | ||
|---- | |---- | ||
|R | |R | ||
|[6] | |[6] | ||
|Incomplete L1 Message | |Incomplete L1 Message | ||
|---- | |---- | ||
|R | |R | ||
|[5] | |[5] | ||
|Unknown Message Address Received | |Unknown Message Address Received | ||
|---- | |---- | ||
|R | |R | ||
|[4] | |[4] | ||
|Double Bit Hamming Error Broadcast. | |Double Bit Hamming Error Broadcast. | ||
|---- | |---- | ||
|R | |R | ||
|[3] | |[3] | ||
|Single Bit Hamming Error Broadcast. | |Single Bit Hamming Error Broadcast. | ||
|---- | |---- | ||
|R | |R | ||
|[2] | |[2] | ||
|Double Bit Hamming Error Individually Addr. | |Double Bit Hamming Error Individually Addr. | ||
|---- | |---- | ||
|R | |R | ||
|[1] | |[1] | ||
|Single Bit Hamming Error Individually Addr. | |Single Bit Hamming Error Individually Addr. | ||
|---- | |---- | ||
|R | |R | ||
|[0] | |[0] | ||
Line 662: | Line 642: | ||
|---- | |---- | ||
|Event_error | |Event_error | ||
| | |0x3053 | ||
|R | |R | ||
|[8:0] | |[8:0] | ||
|Latest Received Event error conditions: | |Latest Received Event error conditions: | ||
|---- | |---- | ||
| | |colspan="2" rowspan="9"| | ||
| | |||
|R | |R | ||
|[8] | |[8] | ||
|NA (= ‘0’) | |NA (= ‘0’) | ||
|---- | |---- | ||
|R | |R | ||
|[7] | |[7] | ||
|L2 message content error | |L2 message content error | ||
|---- | |---- | ||
|R | |R | ||
|[6] | |[6] | ||
|L1 message content error | |L1 message content error | ||
|---- | |---- | ||
|R | |R | ||
|[5] | |[5] | ||
|Prepulse error (=0; possible future use) | |Prepulse error (=0; possible future use) | ||
|---- | |---- | ||
|R | |R | ||
|[4] | |[4] | ||
|NA (= ‘0’) | |NA (= ‘0’) | ||
|---- | |---- | ||
|R | |R | ||
|[3] | |[3] | ||
|NA (= ‘0’) | |NA (= ‘0’) | ||
|---- | |---- | ||
|R | |R | ||
|[2] | |[2] | ||
|L2 message missing/timeout | |L2 message missing/timeout | ||
|---- | |---- | ||
|R | |R | ||
|[1] | |[1] | ||
|L2 message arrives outside legal timeslot | |L2 message arrives outside legal timeslot | ||
|---- | |---- | ||
|R | |R | ||
|[0] | |[0] |
Latest revision as of 07:37, 24 April 2012
Busy Box Status and Control Registers | ||||
---|---|---|---|---|
Name | Address | Mode | Description | Default Value |
TX module(15:0) | 0x0001 | RW | For sending messages to DRORCs.
|
0x0000 |
RX memory | 0x1000-0x1FFF | RW | Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
|
0x0000 |
RX memory pointer(13:0) | 0x2000 | R | Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message. | 0x0000 |
EventID FIFO count(3:0) | 0x2001 | R | Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. | 0x0000 |
Current EventID(35:32) | 0x2002 | R | The EventID which is currently being matched. | 0x0000 |
Current EventID(31:16) | 0x2003 | R | 0x0000 | |
Current EventID(15:0) | 0x2004 | R | 0x0000 | |
Newest EventID(35:32) | 0x2005 | R | The EventID most recently received from the Trigger system. | 0x0000 |
Newest EventID(31:16) | 0x2006 | R | 0x0000 | |
Newest EventID(15:0) | 0x2007 | R | 0x0000 | |
L1 Trigger Timeout(15:0) | 0x2008 | RW | Time in 10 us resolution the 'busy' will be asserted after an L1A trigger. Note: The busy will not be deasserted if the buffers are full. | 0x000A |
Busy Condition(15:0) | 0x2009 | RW | Status and control registers concerning the BUSY generation
|
0x0000 |
Halt FSM matching(0) | 0x200A | RW | If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs. | 0x0001 |
Force match(0) | 0x200B | T | Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect. | N/A |
Re-Request Timeout(15:0) | 0x200C | RW | Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs. | 0x07FF |
Current RequestID(3:0) | 0x200D | R | Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. | 0x0000 |
Retry Count(15:0) | 0x200E | R | Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID. | 0x0000 |
Busy time(31:16) | 0x2010 | R | Holds value of counter for number of clock cycles BUSY has been asserted. | 0x0000 |
Busy time(15:0) | 0x2011 | R | 0x0000 | |
RX mem filter(15:0) | 0x2012 | RW | Allows filtering of messages that are stored in RX memory.
|
0x0000 |
Number of Channels | 0x2014 | R | Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time. | N/A |
Firmware Revision | 0x2015 | R | Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 54 | 0x0036 |
Stresstest Enable(0) | 0x2016 | RW | Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available. | 0x0000 |
Burst Size(5:0) | 0x2017 | RW | The maximum burst size. A value of 0 disables the Burst Interlock feature. Maximum value is 63. | 0x0000 |
Burst Interlock Leak Time(15:0) | 0x2018 | RW | Leak time for the Burst Interlock "leaky bucket" defined in steps of 10 us. Maximum leak time is 655.4 ms. | 0x0000 |
Trigger Mode(2:0) | 0x2019 | RW | Control registers concerning the BUSY/trigger mode
|
0x0000 |
Current Trigger Event Info(12:0) | 0x2050 | R | Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping. | 0x0000 |
Current Trigger Event Error(24:16) | 0x2051 | R | Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping. | 0x0000 |
Current Trigger Event Error(15:0) | 0x2052 | R | Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping. | 0x0000 |
Newest Trigger Event Info(12:0) | 0x2054 | R | Holds the Event Info for newest eventID as reported by the TRM. See TRM registers for bitmapping. | 0x0000 |
Newest Trigger Event Error(24:16) | 0x2055 | R | Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping. | 0x0000 |
Newest Trigger Event Error(15:0) | 0x2056 | R | Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping. | 0x0000 |
Channel Registers | 0x21XX | RW | 'XX' in the address gives the channelnumber in hexadecimal.
|
0x0001 |
Trigger Receiver Module Status and Control Registers | ||||
---|---|---|---|---|
Name | Address | Mode | Bit slice | Description |
Control | 0x3000 | RW | [15:13] | Unused |
RW | [12] | Trigger Input Mask Enable. Default=0 | ||
RW | [11] | L1a message mask. Default=1 | ||
RW | [10] | L2 Timeout FIFO storage mask. Default=1 | ||
RW | [9] | L2r FIFO storage mask. Default=1 | ||
RW | [8] | L2a FIFO storage mask. Default=1 | ||
RW | [7:4] | Unused | ||
RW | [3] | L0 support. Default=1 | ||
RW | [2] | Unused | ||
RW | [1] | Disable_error_masking. Default=0 | ||
RW | [0] | Serial B channel on/off. Default=1 | ||
Control | 0x3001 | R | [15:8] | Trigger Receiver Version. Default=0x16 |
R | [7:4] | CDH version. Default=0x2 | ||
R | [3] | Not used | ||
R | [2] | Busy (receiving sequence) - | ||
R | [1] | Run Active - | ||
R | [0] | Bunch_counter overflow - | ||
Module Reset | 0x3002 | T | N/A | Reset Module |
Reset Counters | 0x3008 | T | N/A | Write to this registers will reset the counters in the module |
Issue Testmode | 0x300A | T | N/A | Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature. |
L1_Latency | 0x300C | RW | [15:12] | Uncertainty region +- N. default value 0x2 (50 ns) |
RW | [11:0] | Latency from L0 to L1. default value 0x0D4 (5.3 us) | ||
L2_Latency MAX | 0x300E | RW | [15:0] | Max Latency from BC0 to L2. default value 0x4E20 (500 us) |
L2_Latency MIN | 0x300F | RW | [15:0] | Min Latency from BC0 to L2. default value 0x0C80 (80 us) |
L1_msg_latency MAX | 0x3014 | RW | [15:0] | Max Latency from BC0 to L1 msg. default value 0x0028 (1 us) |
L1_msg_latency MIN | 0x3015 | RW | [15:0] | Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us) |
Pre_pulse_counter | 0x3016 | R | [15:0] | Number of decoded pre-pulses. |
BCID_Local | 0x3018 | R | [11:0] | Number of bunchcrossings at arrival of L1 trigger. |
L0_counter | 0x301A | R | [15:0] | Number of L0 triggers |
L1_counter | 0x301C | R | [15:0] | Number of L1 triggers |
L1_msg_counter | 0x301E | R | [15:0] | Number of successfully decoded L1 messages |
L2a_counter | 0x3020 | R | [15:0] | Number of successfully decoded L2a messages |
L2r_counter | 0x3022 | R | [15:0] | Number of successfully decoded L2r messages |
Bunchcounter | 0x3026 | R | [11:0] | Debug: Number of bunchcrossings |
SingleHammingErrorCnt | 0x302C | R | [15:0] | Number of single bit hamming errors |
DoubleHammingErrorCnt | 0x302D | R | [15:0] | Number of double bit hamming errors |
MsgDecodingErrorCnt | 0x302E | R | [15:0] | Number of message decoding errors |
SeqTimoutErrorCnt | 0x302F | R | [15:0] | Number of errors related to sequence and timeouts. |
Buffered_events | 0x3040 | R | [4:0] | Number of events stored in the FIFO. |
DAQ_Header01 | 0x3042 | R | [15:0] | Latest received DAQ Header 1 [15:0] |
DAQ_Header01 | 0x3043 | R | [15:0] | Latest received DAQ Header 1 [31:16] |
DAQ_Header02 | 0x3044 | R | [15:0] | Latest received DAQ Header 2 [15:0] |
DAQ_Header02 | 0x3045 | R | [15:0] | Latest received DAQ Header 2 [31:16] |
DAQ_Header03 | 0x3046 | R | [15:0] | Latest received DAQ Header 3 [15:0] |
DAQ_Header03 | 0x3047 | R | [15:0] | Latest received DAQ Header 3 [31:16] |
DAQ_Header04 | 0x3048 | R | [15:0] | Latest received DAQ Header 4 [15:0] |
DAQ_Header04 | 0x3049 | R | [15:0] | Latest received DAQ Header 4 [31:16] |
DAQ_Header05 | 0x304a | R | [15:0] | Latest received DAQ Header 5 [15:0] |
DAQ_Header05 | 0x304b | R | [15:0] | Latest received DAQ Header 5 [31:16] |
DAQ_Header06 | 0x304c | R | [15:0] | Latest received DAQ Header 6 [15:0] |
DAQ_Header06 | 0x304d | R | [15:0] | Latest received DAQ Header 6 [31:16] |
DAQ_Header07 | 0x304e | R | [15:0] | Latest received DAQ Header 7 [15:0] |
DAQ_Header07 | 0x304f | R | [15:0] | Latest received DAQ Header 7 [31:16] |
Event_info | 0x3050 | R | [12:0] | Latest Received Event information: |
R | [12] | Include payload | ||
R | [11] | Event has L2 Accept trigger | ||
R | [10] | Event has L2 Reject trigger | ||
R | [9] | Calibration trigger event | ||
R | [8] | Software trigger event | ||
R | [4:7] | Calibration/SW trigger type (= RoC) | ||
R | [3] | NA(=‘0’) | ||
R | [2] | NA(=‘0’) | ||
R | [1] | Region of Interest announced (=ESR) | ||
R | [0] | NA(=’0’) | ||
Event_error | 0x3052 | R | [15:0] | Latest Received Event error conditions: |
R | [15] | L1 message arrives outside legal timeslot | ||
R | [14] | Missing L1 | ||
R | [13] | Boundary L1 | ||
R | [12] | Spurious L1 | ||
R | [11] | Missing L0 | ||
R | [10] | Spurious L0 | ||
R | [9] | TTCrx Address Error (not X”0003”) | ||
R | [8] | NA (= ‘0’) | ||
R | [7] | Incomplete L2a Message | ||
R | [6] | Incomplete L1 Message | ||
R | [5] | Unknown Message Address Received | ||
R | [4] | Double Bit Hamming Error Broadcast. | ||
R | [3] | Single Bit Hamming Error Broadcast. | ||
R | [2] | Double Bit Hamming Error Individually Addr. | ||
R | [1] | Single Bit Hamming Error Individually Addr. | ||
R | [0] | Serial B Stop Bit Error | ||
Event_error | 0x3053 | R | [8:0] | Latest Received Event error conditions: |
R | [8] | NA (= ‘0’) | ||
R | [7] | L2 message content error | ||
R | [6] | L1 message content error | ||
R | [5] | Prepulse error (=0; possible future use) | ||
R | [4] | NA (= ‘0’) | ||
R | [3] | NA (= ‘0’) | ||
R | [2] | L2 message missing/timeout | ||
R | [1] | L2 message arrives outside legal timeslot | ||
R | [0] | L1 message missing/timeout |