Modelsim/Questa: Difference between revisions
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[[Simulering av VHDL]] | [[Simulering av VHDL]] | ||
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[[Synthese av VHDL]] | [[Synthese av VHDL]] | ||
== Referanselitteratur == | == Referanselitteratur == | ||
[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL] | [http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL] | ||
[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook] | [http://freerangefactory.org/books_tuts.html Free Range VHDL textbook] | ||
[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example] | [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example] | ||
[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)] | [http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)] | ||
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[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer] | [http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer] | ||
[ | [https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ] | ||
[https://github.com/UVVM Bitvis UVVM på GitHub ] | |||
[[Category:Mikroelektronikk]] | [[Category:Mikroelektronikk]] | ||