CZT-firmware

List of included modules in hierachical order:

Detector module interface (dm_if)

interface to readout electroncs for the detector modules. Reads energy, pixel and ASIC address, in addition to multihit information. Also controls the pipelined ADC.

Offset substract

Finds and subtracts the offset from ADC data, ensuring a consistent mean value of zero between all four detector chains

Hit discriminator (hit_dicr)

determines whether there was an event or not?

Memory bus interface (mb_if)

for communication with user interface. including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

input:

• memory address memadr_in (from adress decoder)
• memory data memdat_in (from address decoder, incl. command )
• status register sr[0-3] (from logic module, e.g. tmon)
• clk etc.

output:

• memdat_out (to address decoder, incl. answer)
• control registers cr[0-3] (to logig module, incl. command)

XA config (xa_cfg)

XA register verification (xa_reg_verify)

FSM, ASIC configuration register verifier

RAM (dpram1k8)

RAM to memorize control register, dual port RAM for volatile XA configuration data

piso8_ctrl

FSM