CZT-firmware: Difference between revisions
| Line 36: | Line 36: | ||
===Memory bus interface (mb_if)=== | ===Memory bus interface (mb_if)=== | ||
==XA config (xa_cfg)== | ==XA config (xa_cfg)== | ||
===XA register verification (xa_reg_verify)=== | |||
FSM, ASIC configuration register verifier | |||
===RAM (dpram1k8)=== | |||
RAM to memorize control register, dual port RAM for volatile XA configuration data | |||
===Memory bus interface=== | |||
===piso8_ctrl=== | |||
FSM | |||
==Resync register== | ==Resync register== | ||
==Clock reset (clkrst)== | ==Clock reset (clkrst)== | ||
==Timetag generation (tt_gen)== | ==Timetag generation (tt_gen)== | ||
Revision as of 18:47, 18 October 2010
List of included modules in hierachical order:
Detector module interface (dm_if)
interface to readout electroncs for the detector modules. Reads energy, pixel and ASIC address, in addition to multihit information. Also controls the pipelined ADC.
Offset substract
Finds and subtracts the offset from ADC data, ensuring a consistent mean value of zero between all four detector chains
Hit discriminator (hit_dicr)=
determines whether there was an event or not?
Memory bus interface (mb_if)
MUX (scdp_ch_mux)
FIFO
DPU interface (dpu_if)
xlink_rx
rx register
xlink_tx
tx register
tx control fsm
Address decoder (adrdec_bgo)
Binning control module (BCM) (bin_ctrl_module)
Scdp channel mux
Bin address generator
Bin access control
Swing buffer
Bin module address arbiter
Memory bus interface (mb_if)
RCU master (rcumaster)
LED control
Memory bus interface (mb_if)
XA config (xa_cfg)
XA register verification (xa_reg_verify)
FSM, ASIC configuration register verifier
RAM (dpram1k8)
RAM to memorize control register, dual port RAM for volatile XA configuration data
Memory bus interface
piso8_ctrl
FSM