View source for VHDL

==Modeling concept==
there are 3 domains of  modeling:
* function
* structure
* geometry

each provides a basic modeling concept.

a module e.g. a register is an '''entity''', it's inputs ans outputs are called '''ports'''. 
an '''architecture''' is the internal implementation of an entity. it describes the behavior of an entity. 
architectures includes only '''processes''', collection of actions which are executed in sequences. 

types of action that can be performed: 
* evaluating expressions
* assigning variables and values
* conditional and repeated execution
* subprogram calls

'''''behavioral architecture''''': function of an entity is described in an abstract way. e.g.
<pre>
entity srlatch is
port ( s,r : in  std_logic;
      q,qb : out std_logic);
end srlatch;

architecture behave of calc is
begin
 foo: process
 begin
    Q <= S nand QB;
    QB <= R nand Q;  
 end process  foo;
end architecture behave;
</pre>

'''''structural architecture''''': only interconnecting subsystems

<pre>
entity nand2 is
port(a,b: in  std logic; 
       q: out std_logic);
end nand2;

architecture basic of nand2 is
q <= a nand b after 2 ns;
end architecture nand2;

</pre>

<pre>
entity srlatch is
port( s,r: in  std logic; 
     q,qb: out std_logic);
end srlatch;

architecture struct of srlatch is
signal int_en : std:logic;

sq: entity work.nand2(basic)
port map (
a => s,
b => qb,
q => q);

rq: entity work.nand2(basic)
port map (
a => r,
b => q,
q => qb);

end architecture srlatch
</pre>