This special page shows the last uploaded files.
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Example script.txt
Are033
08:04, 29 September 2022
; 2 KB
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PN ratio 4.png
Are033
09:07, 28 September 2022
2,516 × 1,008; 334 KB
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PN ratio 1.png
Are033
09:04, 28 September 2022
2,554 × 868; 242 KB
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Invert 1.png
Are033
09:05, 14 September 2022
1,244 × 1,104; 97 KB
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Libmanager basic.png
Are033
08:47, 13 September 2022
949 × 526; 47 KB
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Start virt.png
Are033
08:44, 13 September 2022
962 × 462; 106 KB
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Master thesis Wai Chun.pdf
Nfyst
09:55, 30 June 2021
; 12.96 MB
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Corner setup.png
Hbi009
14:07, 7 May 2021
800 × 503; 144 KB
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XJLink Manager.png
Lra034
16:39, 22 February 2021
536 × 442; 19 KB
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XJDemo v3.1.png
Lra034
16:11, 22 February 2021
399 × 246; 209 KB
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Nikolai-thesis-final.pdf
Nfyal
14:15, 11 December 2020
; 9.34 MB
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Higgs2020.pdf
Nfyal
14:15, 10 November 2020
; 26.34 MB
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Grieg-logo.png
Nfyal
23:32, 3 November 2020
1,225 × 640; 1.1 MB
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Puttyx11.png
Bhu006
12:22, 3 May 2020
452 × 442; 17 KB
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Puttylogin.png
Bhu006
12:22, 3 May 2020
452 × 442; 22 KB
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Hierarket.jpg
Gge002
13:29, 29 May 2018
3,170 × 1,801; 638 KB
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Hierarchy editor.png
Put009
15:28, 4 May 2018
700 × 828; 78 KB
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LVS summary.png
Put009
15:00, 4 May 2018
442 × 499; 30 KB
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ASSURA QRC.png
Put009
08:52, 3 May 2018
650 × 811; 108 KB
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Shaper.ps.jpg
Fli091
14:24, 22 March 2018
576 × 319; 22 KB
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CadencePlotOptions.png
Fli091
13:46, 22 March 2018
482 × 413; 44 KB
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CadencePrintWindow.png
Fli091
13:45, 22 March 2018
482 × 635; 51 KB
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Fsbl created.png
Yag005
17:53, 6 December 2017
411 × 174; 15 KB
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Project explorer start.png
Yag005
17:49, 6 December 2017
410 × 201; 13 KB
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Main code.png
Yag005
17:35, 6 December 2017
867 × 407; 53 KB
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AXILedBlink code.png
Yag005
17:32, 6 December 2017
383 × 317; 26 KB
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Remove include demo libs.png
Yag005
17:23, 6 December 2017
696 × 514; 45 KB
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Source folder.png
Yag005
17:05, 6 December 2017
818 × 835; 118 KB
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FreeRTOSConfig cpu freq edit.png
Yag005
15:51, 6 December 2017
915 × 556; 192 KB
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Port c edit.png
Yag005
15:46, 6 December 2017
1,024 × 796; 246 KB
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Lscript id edit.png
Yag005
15:39, 6 December 2017
1,024 × 796; 134 KB
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Led port success.png
Yag005
16:52, 4 December 2017
990 × 641; 24 KB
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S00 1.png
Yag005
16:49, 4 December 2017
1,411 × 678; 90 KB
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S00 2.png
Yag005
16:48, 4 December 2017
1,406 × 674; 82 KB
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Led ip 1.png
Yag005
16:48, 4 December 2017
1,411 × 676; 85 KB
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Led ip 3.png
Yag005
16:48, 4 December 2017
1,407 × 674; 75 KB
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Led ip 2.png
Yag005
16:48, 4 December 2017
1,408 × 675; 94 KB
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Diagram axi4lite periph added.png
Yag005
14:24, 4 December 2017
999 × 636; 68 KB
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Add interfaces axi4lite.png
Yag005
13:44, 4 December 2017
850 × 578; 29 KB
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First block.png
Yag005
14:43, 28 November 2017
998 × 633; 35 KB
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Create block design.png
Yag005
14:33, 28 November 2017
407 × 293; 16 KB
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New project default part.png
Yag005
14:25, 28 November 2017
800 × 703; 41 KB
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New project name.png
Yag005
14:01, 28 November 2017
800 × 703; 24 KB
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Export hardware.png
Yag005
13:46, 28 November 2017
344 × 280; 12 KB
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Launch SDK.png
Yag005
13:42, 28 November 2017
399 × 310; 13 KB
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Root file hierarchy.PNG
Hpe090
08:55, 24 November 2017
1,021 × 374; 32 KB
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Geometry hiarerachy.png
Hpe090
08:55, 24 November 2017
558 × 401; 14 KB
