PHYS321

Fagressurser for bruk i PHYS321

Fagbøker

• Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits

Nettressurser

• Tutorials for Programmable Logic and Military/Aerospace Systems
• Arithmetic Algorithms Simulators
• Linear feedback shift register

Cadence tutorials

• Inverter eksempel
• Inverter eksempel 1 youtube
• Inverter eksempel 2 youtube
• Inverter eksempel 3 youtube

Øvingsoppgaver

Øvingsoppgaver PHYS321

Digilent Nexys 4

• Install Vivado with free licence
• Getting started
• Vivado - Xilinx Programming Environment - Board files, reference projects, etc
• Nexys 4 Resource center

Vivado 2015.4 Install with free licens

• Install

To download Vivado for free you must first create an account. By following this link Xilinx web page you will enter Xilinx download page. For this tutorial we will be using the 2015.4 version.

To download for Windows

Vivado HLx 2015.4 Web Install for Windows with SDK (EXE - 49.32 MB)

For linux

Vivado HLx 2015.4 Web Install for Linux with SDK (BIN - 76.98 MB)

Run the installer and this will show, press next

Type your user name and password and press next

Agree to everything!!! Or else?!?!

Choose Vivado HL WebPACK

Make sure the Software Development Kit, Artix-7, Install Cable Drivers, and Acquire or Manage a License Key are all checked and click next. The DocNav file is not necessary but it allows you to • Find answers to your questions quickly through the integrated search • Manage documents on your desktop through the Download Manager • Always ensures you are reading the latest version of documentation Detailed information about using the tool and its features can be found in the Online Help Menu which you can access after installation.

Choose a directory to Install you Vivado product, make sure you have adequate free space on your hard drive.

The final screen summarizes your selections. Click install, and the installer will begin downloading the files it needs to install Vivado. When it is done this screen will pop up.

Click ok and the license manager should open up. If not open Vivado press Help=>obtain a license key and this window will open. Choose “Get Free SDK, Vivado WebPACK” and then press Connect Now. .

You will be redirected to Xilinx home page were you will need to sign in with user name and password. After clicking “sign in”, press “next” and this site will pop up

Choose “Vivado Design Suite: HL WebPACK, Node-Locked License……..” and press Generate Node-Locked License. Next this window will pop up.

Click next and a new window will pop up, click next again and this will show

Open your E-mail and download the attached Xilinx.lic file. When you go back to the license manager this will show, press cancel.

Go to Load License in the left menu. You should see this

Click Copy License and upload the Xilinx.lic file and you will get this message

If you now press the view license status in the left menu, you should see this

You can now close the license manager and Vivado is good to go.

CREATING NEW PROJECT

Press create new project

Press next on the first window that pops up, then you can choose were you want to store your project, click next.

Choose RTL project and click next

Add your VHDL file if you have one, if you don’t you can add the VGA-controller file just to make sure that everything works properly. Click next

Click next

Add the Nexys4_Master.xdc , this will connect all your I/O, LED, SW etc.

Choose the xca100tcsg324-1 and click next and then finish.

Vivado will open, now you can make your own VHDL code or you can follow instruction further if you want to use the VGA controller. If you want to make your own code you can skip the IP part and go to generate bitstream to see how you should implement your code on the FPGA.

Adding IP’s, clk generator 25.2MHz and BRAM. Click IP Catalog and then

Search for Clocking Wizard and enter and this will pop up, clocking option should look like this, remember to change the Component name!

Change the output clock to 25.2MHz

Port renaming: use names that explains your component, and click OK

This should pop up, click generate

Adding BRAM, search for bram and enter the Block Memory Generator and this should pop up. Remember component name

Port A Options, write width = 12bits, write depth = 307200=(480*640 pixels projected on screen), then click OK and then generate as before and wait until the synthesis is done.

GENERATE BITSTREAM: click generate bitstream

If this pops up click yes

If this message shows, just click ok, it only means that you have pins activated in your Nexys4_Master.xdc that are not in use.

If later on want to change witch pins are active on your board you can configure this by entering the Nexys4_Master.xdc

When completed, choose “Open Hardware Manager” and click ok

At this point connect your NEXY4 board . In the left menu under “program and debug”, click open target => open new target

Open new Hardware target will pop up, click next two times and this will show. Choose JTAG clock freq. 30 000 000, click next and then finish

Now you can program your device, click program device and choose your FPGA

Click program and your device is ready to go.