VHDL - Revision history

Fli091: Added Category:Mikroelektronikk Category:VHDL

2017-09-15T13:16:51Z

Added Category:Mikroelektronikk Category:VHDL

← Older revision		Revision as of 13:16, 15 September 2017
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	</pre>		</pre>

			[[Category:Mikroelektronikk]] [[Category:VHDL]]

Ako054 at 13:15, 1 October 2010

2010-10-01T13:15:12Z

← Older revision		Revision as of 13:15, 1 October 2010
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	in a configuration file the declaration can be made in which case which entity is using which architecture. the architectures may vary e.g. in case of simulation or synthesis.		in a configuration file the declaration can be made in which case which entity is using which architecture. the architectures may vary e.g. in case of simulation or synthesis.
	A '''configuration declaration''' is a design unit which can be compiled separately. In a configuration declaration the binding of all components which are part of a certain entity can be specified.		A '''configuration declaration''' is a design unit which can be compiled separately. In a configuration declaration the binding of all components which are part of a certain entity can be specified.
			also generic maps can be set.

	<pre>		<pre>

Ako054: /* components */

2010-10-01T12:31:01Z

components

← Older revision		Revision as of 12:31, 1 October 2010
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	it is an alternative to use entity declarations (see structural design).		it is an alternative to use entity declarations (see structural design).
	an entity declaration defines a real module, it's a separate design. a component declaration defines a virtual module in the architecture body. "for this architecture we assume there is a module specified by this component".		an entity declaration defines a real module, it's a separate design. a component declaration defines a virtual module in the architecture body. "for this architecture we assume there is a module specified by this component".

			===configurations===
			in a configuration file the declaration can be made in which case which entity is using which architecture. the architectures may vary e.g. in case of simulation or synthesis.
			A '''configuration declaration''' is a design unit which can be compiled separately. In a configuration declaration the binding of all components which are part of a certain entity can be specified.


			<pre>
			configuration config_identifier of entity_name is
			for architecture_name

			for all : component_identifier
			use entity lib_name.entity_name2(architecture_name2); --binding_indication
			end for;

			for bgo_channel_1 : bgo_channel
			use entity mxgs_bgo_lib.bgo_channel(struct)
			generic map(
			g_bgo_channel => "01"
			);
			end for;

			end for;
			end config_identifier;

			</pre>

Ako054 at 14:27, 29 September 2010

2010-09-29T14:27:33Z

← Older revision		Revision as of 14:27, 29 September 2010
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	===components===		===components===
	to build hierarchical designs, used to describe interconnections in subsystems in a design.		to build hierarchical designs, used to describe interconnections in subsystems in a design.
	component declarations are written in the declarative part of the architecture (before the ~~'''~~''begin'''~~'')~~.		component declarations are written in the declarative part of the architecture (before the ''begin'').
			it is an alternative to use entity declarations (see structural design).
			an entity declaration defines a real module, it's a separate design. a component declaration defines a virtual module in the architecture body. "for this architecture we assume there is a module specified by this component".

Ako054: /* components */

2010-09-29T14:10:18Z

components

← Older revision		Revision as of 14:10, 29 September 2010
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	===components===		===components===
			to build hierarchical designs, used to describe interconnections in subsystems in a design.
			component declarations are written in the declarative part of the architecture (before the '''''begin''''').

Ako054 at 13:55, 29 September 2010

2010-09-29T13:55:01Z

← Older revision		Revision as of 13:55, 29 September 2010
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	====procedures====		====procedures====
			variables etc. defined in the header are local variables.
	<pre>		<pre>
	procedure proc_name is		procedure proc_name is
	variable total : real :=0.0;		variable total : real :=0.0; --this is a local variable!
	begin		begin
	for index in samples loop		for index in samples loop
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	the external view is specified in the '''package declaration''', the implementation is defind in the '''package body'''.		the external view is specified in the '''package declaration''', the implementation is defind in the '''package body'''.

	the package declaration hosts type, constand, subprogram, signal ... declarations which are shared within the model. in the model then you just need to refer to the package:		====package declaration====
			the package declaration hosts type, constand, subprogram, signal ... declarations which are shared within the model.
			it defines the interface to a package. in the model then you just need to refer to the package:
	<pre>		<pre>
	package yourpackagename is --declaration		package yourpackagename is --declaration
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	end entity yourentityname;		end entity yourentityname;
	</pre>		</pre>

			====package body====
			no package body is needed if pkg declaration contains other kinds of declarations like types, signals or fully specified constants. in case of subprograms body needed to fill in missing informations.

			items declared in body must include full declaration of subprograms as they are in the pkg declaration. that means that types, modes, default constants... must bee repeated exactly.

			===components===

Ako054 at 13:30, 29 September 2010

2010-09-29T13:30:29Z

← Older revision		Revision as of 13:30, 29 September 2010
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	<pre>		<pre>
	proc_name;		proc_name;
	</~~per~~>		</pre>

	it is possible to use procedures with parameters.		it is possible to use procedures with parameters.

Ako054 at 13:29, 29 September 2010

2010-09-29T13:29:46Z

@@ Line 76: / Line 76: @@
 end architecture struct;
 </pre>
 ===Packages===
@@ Line 81: / Line 126: @@
 grouping  a collection of related declarations to serve common purpose.
 seperat design units that can be worked on independently, reused in different parts of design.
 the external view is specified in the '''package declaration''', the implementation is defind in the '''package body'''.

Ako054 at 09:41, 29 September 2010

2010-09-29T09:41:49Z

← Older revision		Revision as of 09:41, 29 September 2010
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	end architecture struct;		end architecture struct;
			</pre>

			===Packages===

			grouping a collection of related declarations to serve common purpose.
			seperat design units that can be worked on independently, reused in different parts of design.

			the external view is specified in the '''package declaration''', the implementation is defind in the '''package body'''.

			the package declaration hosts type, constand, subprogram, signal ... declarations which are shared within the model. in the model then you just need to refer to the package:
			<pre>
			package yourpackagename is --declaration
			constant foo: std_logic_vector(7 downto 0) := X"01";
			type foobar is array (foobar2) of somethingelse;
			end package yourpackagename;
			</pre>
			<pre>
			use yourpackagename.all;

			entity yourentityname is
			port (
			fooport : in work.yourpackagename.foo;
			foobarport : in work.yourpackagename.foobar;
			);
			end entity yourentityname;
	</pre>		</pre>

Ako054 at 17:50, 28 September 2010

2010-09-28T17:50:22Z

← Older revision		Revision as of 17:50, 28 September 2010
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	<pre>		<pre>
			LIBRARY ieee;
			USE ieee.std_logic_1164.ALL;

	entity nand2 is		entity nand2 is
	port(a,b: in ~~std logic~~;		port(
	q: out std_logic);		a,b : in std_logic;
			q : out std_logic);
	end nand2;		end nand2;

	architecture basic of nand2 is		architecture basic of nand2 is
			begin
	q <= a nand b after 2 ns;		q <= a nand b after 2 ns;
	end ~~architecture nand2~~;		end basic;

	</pre>		</pre>

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	architecture struct of srlatch is		architecture struct of srlatch is
			begin
	sq: entity work.nand2(basic)		sq: entity work.nand2(basic)
	port map (		port map (
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	);		);

	end architecture ~~srlatch~~		end architecture struct;
	</pre>		</pre>