SmartFusion2- AMBA APB, Custom Peripheral - Revision history

Cto070 at 12:50, 22 October 2013

2013-10-22T12:50:15Z

← Older revision		Revision as of 12:50, 22 October 2013
Line 192:		Line 192:
	Go to ''Project'', ''Project Settings'', ''Device I/O Settings'' and set ''Default I/O Technology'' to ''LVCMOS 3.3V''.		Go to ''Project'', ''Project Settings'', ''Device I/O Settings'' and set ''Default I/O Technology'' to ''LVCMOS 3.3V''.

	Import the Physical Design Constraint file supplied below. Name it Fabric_top.io.		Import the Physical Design Constraint file supplied below. Name it Fabric_top.pdc.

	# Microsemi I/O Physical Design Constraints file		# Microsemi I/O Physical Design Constraints file

Cto070 at 11:21, 22 October 2013

2013-10-22T11:21:22Z

← Older revision		Revision as of 11:21, 22 October 2013
Line 762:		Line 762:
	reset_n : in std_logic; -- asynch reset, negative polarity		reset_n : in std_logic; -- asynch reset, negative polarity


	global_reset : in std_logic; -- global reset, positive polarity		global_reset : in std_logic; -- global reset, positive polarity
	rcu_reset : in std_logic; -- reset for RCU Xilinx fw, positive polarity		rcu_reset : in std_logic; -- reset for RCU Xilinx fw, positive polarity

Cto070 at 09:32, 30 September 2013

2013-09-30T09:32:32Z

← Older revision		Revision as of 09:32, 30 September 2013
Line 424:		Line 424:
	Build Debug Application by pressing ''Debug Configurations'' and then choose ''Microsemi Cortex M3 Target''. Press ''Apply'', build debug target and launch debug target. <br>		Build Debug Application by pressing ''Debug Configurations'' and then choose ''Microsemi Cortex M3 Target''. Press ''Apply'', build debug target and launch debug target. <br>
	[[File:Debug_configuration.jpg\|600 px]]<br>[[File:Debugging.jpg\|600px]]<br>[[File:Debug_binary_count.jpg\|600px]]<br>		[[File:Debug_configuration.jpg\|600 px]]<br>[[File:Debugging.jpg\|600px]]<br>[[File:Debug_binary_count.jpg\|600px]]<br>

			=VHDL files=

	-------------------------------------------------------------------------------		-------------------------------------------------------------------------------

Cto070 at 09:30, 30 September 2013

2013-09-30T09:30:19Z

Show changes

Cto070 at 09:14, 30 September 2013

2013-09-30T09:14:13Z

← Older revision		Revision as of 09:14, 30 September 2013
Line 63:		Line 63:

	# add your BFM commands below:		# add your BFM commands below:

	memmap apb_to_dcs_0 0x50000000;		memmap apb_to_dcs_0 0x50000000;

Cto070 at 09:13, 30 September 2013

2013-09-30T09:13:38Z

@@ Line 31: / Line 31: @@
 [[File:Chip_osc.jpg|500 px]][[File:CCC_core.jpg|400 px]]<br>
-Now import all the vhdl files [[Media:APB_DCS_files.zip]] by clicking ''File'',  ''Import'', ''HDL Source Files''. These files can now be found under ''hdl'' in the ''Files'' tab and in ''Design Hierarchy''. In ''Design Hierarchy'' right click on ''DCS_test'', choose ''Create Core from HDL''. Answer ''No'' to question about adding bus interfaces to core. Right click on ''apb_to_dcs'' and choose ''Create Core from HDL''. Choose ''Yes'' on question about adding bus interfaces to core. Choose ''Add/Edit bus interfaces...''. In next window, click ''Add Bus Interface...'', choose ''APB, AMBA, AMBA2, slave''. Connect ''PSELx'' to ''psel''.<br> [[File:Module_bus_interface.jpg|500 px]]
+Now import all the vhdl files which are included at the bottom of the page. Save the files with the names specified in the text. The files can be included by clicking ''File'',  ''Import'', ''HDL Source Files''. These files can now be found under ''hdl'' in the ''Files'' tab and in ''Design Hierarchy''. In ''Design Hierarchy'' right click on ''DCS_test'', choose ''Create Core from HDL''. Answer ''No'' to question about adding bus interfaces to core. Right click on ''apb_to_dcs'' and choose ''Create Core from HDL''. Choose ''Yes'' on question about adding bus interfaces to core. Choose ''Add/Edit bus interfaces...''. In next window, click ''Add Bus Interface...'', choose ''APB, AMBA, AMBA2, slave''. Connect ''PSELx'' to ''psel''.<br> [[File:Module_bus_interface.jpg|500 px]]
 Add the modules you made to the SmartDesign. In design canvas, right click and choose ''Auto Connect'' followed by ''Auto Arrange Instances''. Right click on ''MSS_RESET_N_F2M'' and ''GPIO_FABRIC'' and select ''Promote to Top Level''. Right click on ''reset_from_siu'' and choose ''Tie Low''. Connect the unconnected wires. The result should look something like the image below<br> [[File:SmartDesign_finished.jpg|700 px]]
@@ Line 38: / Line 38: @@
 =Pre-synthesized Simulation=
-To simulate the functionality of the abp_to_dcs module, normal APB bus functionality from the MSS should be used. To do this you can add a .bfm file (Bus Functional Model). In the supplied files there is a file called User.bfm. Copy the content of this file to the User.bfm in your project, located under ''Files'' and ''simulation''.
+ #===========================================================
 Next, go to ''Project'' and then ''Project Settings''. Choose ''DO File'' under ''Simulation Options''. You can use the run.do file supplied in the .zip. If you want to use automatic .do file and add signals yourself you can use standard settings, but be sure to change simulation time to 150 us. The system has got some initialization time, which takes around 120 us with this setup, before the bus signals start to change.

Cto070 at 09:02, 30 September 2013

2013-09-30T09:02:10Z

Show changes

Cto070 at 08:24, 30 September 2013

2013-09-30T08:24:50Z

← Older revision		Revision as of 08:24, 30 September 2013
Line 60:		Line 60:
	Build Debug Application by pressing ''Debug Configurations'' and then choose ''Microsemi Cortex M3 Target''. Press ''Apply'', build debug target and launch debug target. <br>		Build Debug Application by pressing ''Debug Configurations'' and then choose ''Microsemi Cortex M3 Target''. Press ''Apply'', build debug target and launch debug target. <br>
	[[File:Debug_configuration.jpg\|600 px]]<br>[[File:Debugging.jpg\|600px]]<br>[[File:Debug_binary_count.jpg\|600px]]<br>		[[File:Debug_configuration.jpg\|600 px]]<br>[[File:Debugging.jpg\|600px]]<br>[[File:Debug_binary_count.jpg\|600px]]<br>

			[[Category:Mikroelektronikk]]

Cto070 at 07:56, 30 September 2013

2013-09-30T07:56:07Z

← Older revision		Revision as of 07:56, 30 September 2013
Line 9:		Line 9:
	=Create new project=		=Create new project=

	Start Libero SoC v11.1. Press ''Project'' and ''New Project''. Name your project ''APB_custom_peripheral''. Use system tools ''SmartFusion2 Microcontroller Subsystem (MSS)''. [[File:New_project.jpg\|400 px]]		Start Libero SoC v11.1. Press ''Project'' and ''New Project''. Name your project ''APB_custom_peripheral''. Use system tools ''SmartFusion2 Microcontroller Subsystem (MSS)''. <br>[[File:New_project.jpg\|400 px]]

	=Modify MSS=		=Modify MSS=

	Double click on the MSS component to modify it. A new window will open. Enable/Disable peripherals until your MSS looks like the image below. <br>		Double click on the MSS component to modify it. A new window will open. Enable/Disable peripherals until your MSS looks like the image below. <br>
	Tip: click ''View > Maximize Work Area'' or ''CTRL+W'' to expand the working area while enabling and disabling the MSS peripherals. [[File:Modified_MSS.jpg\|600 px]]		Tip: click ''View > Maximize Work Area'' or ''CTRL+W'' to expand the working area while enabling and disabling the MSS peripherals.<br> [[File:Modified_MSS.jpg\|600 px]]

	Click on the configuration button for the enabled peripherals, and configure them like the following images<br>		Click on the configuration button for the enabled peripherals, and configure them like the following images<br>
Line 33:		Line 33:
	Now import all the vhdl files [[Media:APB_DCS_files.zip]] by clicking ''File'', ''Import'', ''HDL Source Files''. These files can now be found under ''hdl'' in the ''Files'' tab and in ''Design Hierarchy''. In ''Design Hierarchy'' right click on ''DCS_test'', choose ''Create Core from HDL''. Answer ''No'' to question about adding bus interfaces to core. Right click on ''apb_to_dcs'' and choose ''Create Core from HDL''. Choose ''Yes'' on question about adding bus interfaces to core. Choose ''Add/Edit bus interfaces...''. In next window, click ''Add Bus Interface...'', choose ''APB, AMBA, AMBA2, slave''. Connect ''PSELx'' to ''psel''.<br> [[File:Module_bus_interface.jpg\|500 px]]		Now import all the vhdl files [[Media:APB_DCS_files.zip]] by clicking ''File'', ''Import'', ''HDL Source Files''. These files can now be found under ''hdl'' in the ''Files'' tab and in ''Design Hierarchy''. In ''Design Hierarchy'' right click on ''DCS_test'', choose ''Create Core from HDL''. Answer ''No'' to question about adding bus interfaces to core. Right click on ''apb_to_dcs'' and choose ''Create Core from HDL''. Choose ''Yes'' on question about adding bus interfaces to core. Choose ''Add/Edit bus interfaces...''. In next window, click ''Add Bus Interface...'', choose ''APB, AMBA, AMBA2, slave''. Connect ''PSELx'' to ''psel''.<br> [[File:Module_bus_interface.jpg\|500 px]]

	Add the modules you made to the SmartDesign. In design canvas, right click and choose ''Auto Connect'' followed by ''Auto Arrange Instances''. Right click on ''MSS_RESET_N_F2M'' and ''GPIO_FABRIC'' and select ''Promote to Top Level''. Right click on ''reset_from_siu'' and choose ''Tie Low''. Connect the unconnected wires. The result should look something like the image below [[File:SmartDesign_finished.jpg\|700 px]]		Add the modules you made to the SmartDesign. In design canvas, right click and choose ''Auto Connect'' followed by ''Auto Arrange Instances''. Right click on ''MSS_RESET_N_F2M'' and ''GPIO_FABRIC'' and select ''Promote to Top Level''. Right click on ''reset_from_siu'' and choose ''Tie Low''. Connect the unconnected wires. The result should look something like the image below<br> [[File:SmartDesign_finished.jpg\|700 px]]

	Generate component by clicking ''SmartDesign'' and ''Generate Component''.		Generate component by clicking ''SmartDesign'' and ''Generate Component''.

Cto070 at 06:40, 30 September 2013

2013-09-30T06:40:04Z

← Older revision		Revision as of 06:40, 30 September 2013
Line 31:		Line 31:
	[[File:Chip_osc.jpg\|500 px]][[File:CCC_core.jpg\|400 px]]<br>		[[File:Chip_osc.jpg\|500 px]][[File:CCC_core.jpg\|400 px]]<br>

	Now import the vhdl files [[Media:APB_DCS_files.zip]] by clicking ''File'', ''Import'', ''HDL Source Files''. These files can now be found under ''hdl'' in the ''Files'' tab and in ''Design Hierarchy''. In ''Design Hierarchy'' right click on ''DCS_test'', choose ''Create Core from HDL''. Answer ''No'' to question about adding bus interfaces to core. Right click on ''apb_to_dcs'' and choose ''Create Core from HDL''. Choose ''Yes'' on question about adding bus interfaces to core. Choose ''Add/Edit bus interfaces...''. In next window, click ''Add Bus Interface...'', choose ''APB, AMBA, AMBA2, slave''. Connect ''PSELx'' to ''psel''.<br> [[File:Module_bus_interface.jpg\|500 px]]		Now import all the vhdl files [[Media:APB_DCS_files.zip]] by clicking ''File'', ''Import'', ''HDL Source Files''. These files can now be found under ''hdl'' in the ''Files'' tab and in ''Design Hierarchy''. In ''Design Hierarchy'' right click on ''DCS_test'', choose ''Create Core from HDL''. Answer ''No'' to question about adding bus interfaces to core. Right click on ''apb_to_dcs'' and choose ''Create Core from HDL''. Choose ''Yes'' on question about adding bus interfaces to core. Choose ''Add/Edit bus interfaces...''. In next window, click ''Add Bus Interface...'', choose ''APB, AMBA, AMBA2, slave''. Connect ''PSELx'' to ''psel''.<br> [[File:Module_bus_interface.jpg\|500 px]]

	Add the modules you made to the SmartDesign. In design canvas, right click and choose ''Auto Connect'' followed by ''Auto Arrange Instances''. Right click on ''MSS_RESET_N_F2M'' and ''GPIO_FABRIC'' and select ''Promote to Top Level''. Right click on ''reset_from_siu'' and choose ''Tie Low''. Connect the unconnected wires. The result should look something like the image below [[File:SmartDesign_finished.jpg\|700 px]]		Add the modules you made to the SmartDesign. In design canvas, right click and choose ''Auto Connect'' followed by ''Auto Arrange Instances''. Right click on ''MSS_RESET_N_F2M'' and ''GPIO_FABRIC'' and select ''Promote to Top Level''. Right click on ''reset_from_siu'' and choose ''Tie Low''. Connect the unconnected wires. The result should look something like the image below [[File:SmartDesign_finished.jpg\|700 px]]