Modelsim/Questa - Revision history

Nfyku: /* Referanselitteratur */

2021-02-04T21:13:27Z

Referanselitteratur

← Older revision		Revision as of 21:13, 4 February 2021
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	[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]		[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]

	~~<!--~~
	~~[http://www.ashenden.com.au/ Ashenden Designs]~~
	~~dead link~~
	~~-->~~
	[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]		[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]

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	[https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ]		[https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ]

			[https://github.com/UVVM Bitvis UVVM på GitHub ]

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]

2021-02-04T21:02:47Z

@@ Line 1: / Line 1: @@
 [[Simulering av VHDL]]
@@ Line 14: / Line 4: @@
 [[Synthese av VHDL]]
 == Referanselitteratur ==
@@ Line 28: / Line 16: @@
 [http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]
 [http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)]

2019-01-23T13:06:13Z

Oppdatert til bitvis UVVM

← Older revision		Revision as of 13:06, 23 January 2019
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	[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]		[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]

	[~~http~~://bitvis.no/~~products~~/~~bitvis-utility-library~~/ Bitvis ~~utility library~~]		[https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ]

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]

2018-03-13T12:38:41Z

Updated a dead link

← Older revision		Revision as of 12:38, 13 March 2018
Line 20:		Line 20:
	[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]		[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]

	[http://www.ashenden.com.au/ Ashenden Designs]		<!--
			[http://www.ashenden.com.au/ Ashenden Designs]
			dead link
			-->
	[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]		[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]

	[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]		[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]

	[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)]		<!--
			[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)]
			dead link
			-->
			[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)]

	[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]		[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]

2017-02-02T13:42:14Z

← Older revision		Revision as of 13:42, 2 February 2017
Line 1:		Line 1:
			<!--
	Mapping av alterabibliotek:		Mapping av alterabibliotek:
	<pre>		<pre>
Line 6:		Line 7:
	vmap altera_mf /prog/altera/vhdl_libs/altera_mf		vmap altera_mf /prog/altera/vhdl_libs/altera_mf
	</pre>		</pre>
			-->

	[[Simulering av VHDL]]		[[Simulering av VHDL]]

2017-01-18T09:28:27Z

← Older revision		Revision as of 09:28, 18 January 2017
Line 19:		Line 19:

	[http://www.ashenden.com.au/ Ashenden Designs]		[http://www.ashenden.com.au/ Ashenden Designs]

			[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]

	[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]		[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]

2016-03-24T11:21:00Z

2015-03-18T10:58:48Z

← Older revision		Revision as of 10:58, 18 March 2015
Line 14:		Line 14:

	== Referanselitteratur ==		== Referanselitteratur ==
	[[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]]		[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]

	[[http://www.ashenden.com.au/ Ashenden Designs]]		[http://www.ashenden.com.au/ Ashenden Designs]

	[[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]]		[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]

	[[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)]]		[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)]

	[[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]]		[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]

	[[http://m.eet.com/media/1151614/23798-46098.pdf 10 tips for generating reusable VHDL]]		[http://m.eet.com/media/1151614/23798-46098.pdf 10 tips for generating reusable VHDL]

	[[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide]]		[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide]

	[[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]]		[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]
	[[http://bitvis.no/products/bitvis-utility-library/ Bitvis utility library]]
			[http://bitvis.no/products/bitvis-utility-library/ Bitvis utility library]

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]

2015-03-18T10:57:29Z

Changed from Cyclone III to Cyclone V

← Older revision		Revision as of 10:57, 18 March 2015
Line 1:		Line 1:
	Mapping av alterabibliotek:		Mapping av alterabibliotek:
	<pre>		<pre>
	vmap ~~cycloneiii~~ /prog/altera/vhdl_libs/~~cycloneiii~~		vmap cyclonev /prog/altera/vhdl_libs/cyclonev
	vmap lpm /prog/altera/vhdl_libs/lpm		vmap lpm /prog/altera/vhdl_libs/lpm
	vmap altera /prog/altera/vhdl_libs/altera		vmap altera /prog/altera/vhdl_libs/altera

2015-01-21T10:40:37Z

← Older revision		Revision as of 10:40, 21 January 2015
Line 24:		Line 24:
	[[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]]		[[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim]]

	[[http://~~www~~.~~edn~~.com/~~contents~~/~~images~~/46098.pdf 10 tips for generating reusable VHDL]]		[[http://m.eet.com/media/1151614/23798-46098.pdf 10 tips for generating reusable VHDL]]

	[[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide]]		[[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide]]

	[[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]]		[[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]]
			[[http://bitvis.no/products/bitvis-utility-library/ Bitvis utility library]]

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]