Layout XL and IHP SG13S - Revision history

Hbi009: /* Post layout simulation */

2021-05-07T14:29:09Z

Post layout simulation

← Older revision		Revision as of 14:29, 7 May 2021
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	Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.		Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.

	If you want to simulate corners with the ptap1 and ntap1 components, you have to add two additional model files for your corner simulation. ~~The~~ model files for IHP 130nm process is located in /eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/tech/SG13_PASSIVES/spectre/		If you want to simulate corners with the ptap1 and ntap1 components, you have to add two additional model files for your corner simulation. These model files for IHP 130nm process is located in /eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/tech/SG13_PASSIVES/spectre/

	Add SG13_cornerCAP.scs and SG13_cornerRES.scs to your model files and click ok. Now you can add bcs(Best Case Scenario) and wcs (Worst Case Scenario) to each corner, remember to enable the "tick box" for each of them. When you are done, the corner setup should look something like this:		Add SG13_cornerCAP.scs and SG13_cornerRES.scs to your model files and click ok. Now you can add bcs(Best Case Scenario) and wcs (Worst Case Scenario) to each corner, remember to enable the "tick box" for each of them. When you are done, the corner setup should look something like this:

Hbi009: /* Post layout simulation */

2021-05-07T14:08:18Z

Post layout simulation

← Older revision		Revision as of 14:08, 7 May 2021
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	Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.		Then Launch -> ADE L to get the simulation setup. Setup -> Design and choose the config file from the test bench cell. Use the stimuli button to create the stimuli (copy the stimuli from the schematic simulation) for the test, and then run it.

			If you want to simulate corners with the ptap1 and ntap1 components, you have to add two additional model files for your corner simulation. The model files for IHP 130nm process is located in /eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/tech/SG13_PASSIVES/spectre/

			Add SG13_cornerCAP.scs and SG13_cornerRES.scs to your model files and click ok. Now you can add bcs(Best Case Scenario) and wcs (Worst Case Scenario) to each corner, remember to enable the "tick box" for each of them. When you are done, the corner setup should look something like this:

			[[File:Corner_setup.png\|400px]]

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]

Nfyku at 09:19, 15 October 2020

2020-10-15T09:19:12Z

← Older revision		Revision as of 09:19, 15 October 2020
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	= Before starting layout =		= Before starting layout =

	Read the Design Kit User Guide. ~~The user guide "SG13_user_guide.pdf"~~ can ~~be also~~ be found in the folder "/eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/doc/pdf/" on the ~~microserver~~.		Read the Design Kit User Guide. It can be found on the SG13SFeatures tab on the Virtuoso console window, or in the folder "/eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/doc/pdf/" on the mikroserver. Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.
	Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.

	~~[[File:SG13 Design Kit User Guide~~.~~pdf]]~~		Other documents are found in "eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/doc/html/"

	~~[[File:SG13 Layout rules~~.~~pdf]]~~

	~~[[File:Documentation.png\|200px]]~~

	If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed").		If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed").

Nfyku at 08:07, 15 October 2020

2020-10-15T08:07:40Z

← Older revision		Revision as of 08:07, 15 October 2020
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	= Before starting layout =		= Before starting layout =

	Read the Design Kit User Guide. The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/~~SG13S_616_rev1~~.0~~.2_a~~/doc/pdf" on the microserver.		Read the Design Kit User Guide. The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_618_rev1.12.0/doc/pdf/" on the microserver.
	Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.		Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.

Bhu006 at 11:11, 1 May 2020

2020-05-01T11:11:03Z

← Older revision		Revision as of 11:11, 1 May 2020
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	[[File:sram.png\|600px]]		[[File:sram.png\|600px]]

			Note that there is a specified minimum enclosure in the design rules for vias between polysilicon and metal. This is because during the manufacturing process, the polysilicon and metal layers are created separately and the alignment is not perfect, so the polysilicon connection must be slightly larger to accommodate the potential offset between these layers. Enclosures can be seen by the polysilicon squares on the vias connecting the Q and Q_B lines in the design above. To set a via enclosure size, right click the via and go to properties. On the bottom, there is a setting for GatPoly enclosure. You must set each direction separately.

	= DRC =		= DRC =

Bhu006 at 12:49, 29 April 2020

2020-04-29T12:49:38Z

← Older revision		Revision as of 12:49, 29 April 2020
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	This is covered in chapter 14 of the user guide. Before you run the QRC, the LVS has to match.		This is covered in chapter 14 of the user guide. Before you run the QRC, the LVS has to match.

	To do an extraction of your circuit click Assura -> Run Quantus ~~QRC~~. In "Setup Dir" make sure the path is set to "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/Assura_SG13/qrc", where the technology files for the qrc run is. Set the "Parasitic Res Component" to "presistor ivpcell SG13_dev" and the "Parasitic Cap Component" to "pcapacitor ivpcell SG13_dev". ~~The~~ run the QRC.		To do an extraction of your circuit click Assura -> Run Quantus. In "Setup Dir" make sure the path is set to "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/Assura_SG13/qrc", where the technology files for the qrc run is. Set the "Parasitic Res Component" to "presistor ivpcell SG13_dev" and the "Parasitic Cap Component" to "pcapacitor ivpcell SG13_dev". Open the Extraction tab and set your ground net (gnd!) in the "Reference node" box. Then run the QRC by pressing OK.

	[[File:ASSURA_QRC.png\|400px]]		[[File:ASSURA_QRC.png\|400px]]

Bhu006 at 09:48, 27 April 2020

2020-04-27T09:48:07Z

← Older revision		Revision as of 09:48, 27 April 2020
Line 1:		Line 1:
	= Before starting layout =		= Before starting layout =

	Read the Design Kit User Guide. ~~Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.~~		Read the Design Kit User Guide. The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/doc/pdf" on the microserver.
	The user guide "SG13_user_guide.pdf" can be also be found in the folder "/eda/design_kits/ihp_sg13/SG13S_616_rev1.0.2_a/doc/pdf" on the microserver.		Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.

			[[File:SG13 Design Kit User Guide.pdf]]

			[[File:SG13 Layout rules.pdf]]

	[[File:Documentation.png\|200px]]		[[File:Documentation.png\|200px]]

	If ~~your~~ laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed").		If you're laying out just one cell (in our case a SRAM-cell) make sure it contains defined values and not just pPar("")-values. This makes it easier to produce the right transistor-sizes etc. If you do not want to change your schematic, make a copy to another cell (e.g. from "sram" to "sram-fixed").

	= Layout XL =		= Layout XL =

Put009: Added Parasitic extraction QRC and Post Layout Simulation

2018-05-04T15:47:57Z

Added Parasitic extraction QRC and Post Layout Simulation

@@ Line 2: / Line 2: @@
 Read the Design Kit User Guide. Especially the part of connecting the substrate (chapter 8.2) and layout (chapter 9). Also make sure you understand the Layout Rules document.
 [[File:Documentation.png|200px]]
@@ Line 9: / Line 10: @@
 = Layout XL =
 From the schematic click Launch -> Layout XL to open the layout environment.
 [[File:layout.png|200px]] [[File:layout2.png|200px]]
@@ Line 68: / Line 69: @@
 = LVS =
-Run LVS by pressing Assura -> Run LVS.
+This is covered in chapter 12 of the user guide.
 [[Category:Mikroelektronikk]]

Fli091: Added Category:Mikroelektronikk

2017-09-15T13:14:29Z

Added Category:Mikroelektronikk

← Older revision		Revision as of 13:14, 15 September 2017
Line 69:		Line 69:

	Run LVS by pressing Assura -> Run LVS.		Run LVS by pressing Assura -> Run LVS.

			[[Category:Mikroelektronikk]]

Ogr043 at 11:46, 12 April 2016

2016-04-12T11:46:30Z

← Older revision		Revision as of 11:46, 12 April 2016
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	[[File:drcok.png\|200px]]		[[File:drcok.png\|200px]]

	The DRC should also be run for ~~Rule Set: Fill and~~ Density.		The DRC should also be run for Density. See IHP user guide for how to produce dummy metal to fill the design.

	= LVS =		= LVS =

	Run LVS by pressing Assura -> Run LVS.		Run LVS by pressing Assura -> Run LVS.