Get readout box up and running - Revision history

Sya081 at 17:56, 8 April 2014

2014-04-08T17:56:44Z

← Older revision		Revision as of 17:56, 8 April 2014
Line 255:		Line 255:
	3 OFF (M0 = 0)		3 OFF (M0 = 0)
	2 OFF (CS_SEL = 0) // Select Platform flash access		2 OFF (CS_SEL = 0) // Select Platform flash access
	1 ~~OFF~~ (EXT_CCLK = 0)		1 ON (EXT_CCLK = 1)
	</pre>		</pre>
	===Burn bootloader and Linux image===		===Burn bootloader and Linux image===

Sya081 at 15:49, 1 March 2012

2012-03-01T15:49:17Z

← Older revision		Revision as of 15:49, 1 March 2012
Line 183:		Line 183:
	Notes:		Notes:
	*Chip_enable: 1=enable;0=disable. LSB = chip 1;		*Chip_enable: 1=enable;0=disable. LSB = chip 1;
	*Readout_clk_src: ~~b'00~~=chip1(J10); ~~b'10~~=chip2(J11); ~~b'01~~=chip3(J13); ~~b'11~~=chip4(J12). LSB = Layer 1		*Readout_clk_src: 0b00=chip1(J10); 0b10=chip2(J11); 0b01=chip3(J13); 0b11=chip4(J12). LSB = Layer 1
	*Frame_sync_src: 0=layer1...5=layer6. Make sure there is a working MK_CLKD signal for the selected layer.		*Frame_sync_src: 0=layer1...5=layer6. Make sure there is a working MK_CLKD signal for the selected layer.
	Slow control parameters will be saved inside Spartan FPGAs, so normally only one time of slow control operation is needed.		Slow control parameters will be saved inside Spartan FPGAs, so normally only one time of slow control operation is needed.

Sya081 at 11:03, 1 March 2012

2012-03-01T11:03:49Z

← Older revision		Revision as of 11:03, 1 March 2012
Line 119:		Line 119:
	</pre>		</pre>
	The above steps can also be done from a telnet terminal, after being initiated, the ssh server is running, you can connect the box from another pc with ssh connection.		The above steps can also be done from a telnet terminal, after being initiated, the ssh server is running, you can connect the box from another pc with ssh connection.

			===Startup scripts===
			For the automatic running of the user initialization scripts, you can't add them directly to the romfs script files like /etc/rc.sysinit, because there files are generated every time during Petalinux compilation and all custom modification will be overwritten. The source files for these initialization scrips are located in "~petalinux-dist/user/sys_init/data/etc/rc", normally you should put your custom startup commands in "start" file, but according to the Makefile, this file doesn't work properly at the moment, so we add our scripts to the end of "sysinit" file:
			<pre>
			echo "Running user init scripts."
			/home/test/init.sh
			</pre>
			After running "make romfs", you will find that these scripts are added into the romfs file "/etc/rc.sysinit".

	==Running DAQ==		==Running DAQ==

Sya081 at 09:27, 1 March 2012

2012-03-01T09:27:11Z

← Older revision		Revision as of 09:27, 1 March 2012
Line 255:		Line 255:
	U-Boot-PetaLinux> run update_kernel		U-Boot-PetaLinux> run update_kernel
	</pre>		</pre>

			==LED definitions==
			* D1: on: Test pattern out mode (mode 2) of Spartan1, off: normal mode;
			* D2: on: All enabled channels have correct patterns, off: at least one channel(1/4 of a chip) of pattern mismatch;
			* D3: flash: 1Hz from Spartan1 to Spartan2, maybe soldered up side down for some boxes;
			* D4: As D1, for Spartan2;
			* D5: As D2, for Spartan2;

	==Useful links==		==Useful links==
	# [http://www.xilinx.com/support/documentation/boards_and_kits/ug533.pdf Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit]		# [http://www.xilinx.com/support/documentation/boards_and_kits/ug533.pdf Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit]

Sya081 at 16:40, 23 February 2012

2012-02-23T16:40:00Z

← Older revision		Revision as of 16:40, 23 February 2012
Line 1:		Line 1:
	==Overview==		==Overview==
			This page contains step by step informations to setup the Focal readout electronics for MAPS detectors.

	==Hardware requirements==		==Hardware requirements==

Sya081 at 16:12, 23 February 2012

2012-02-23T16:12:36Z

← Older revision		Revision as of 16:12, 23 February 2012
Line 229:		Line 229:
	1 OFF (EXT_CCLK = 0)		1 OFF (EXT_CCLK = 0)
	</pre>		</pre>

			For the switch setups, please refer to [http://www.xilinx.com/support/documentation/boards_and_kits/ug534.pdf ML605 Hardware User Guide].

	===Program the Platform flash===		===Program the Platform flash===
Line 252:		Line 254:
	U-Boot-PetaLinux> run update_kernel		U-Boot-PetaLinux> run update_kernel
	</pre>		</pre>
			==Useful links==
			# [http://www.xilinx.com/support/documentation/boards_and_kits/ug533.pdf Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit]
			# [http://www.xilinx.com/support/documentation/boards_and_kits/xtp055.pdf ML605 Restoring Flash Contents]
			# [http://www.xilinx.com/support/documentation/user_guides/ug360.pdf Virtex-6 FPGA Configuration User Guide]

	[[Category:Focal]]		[[Category:Focal]]

Sya081 at 16:02, 23 February 2012

2012-02-23T16:02:51Z

← Older revision		Revision as of 16:02, 23 February 2012
Line 235:		Line 235:
	S1:		S1:
	4 OFF (SysACE Mode = 0) // Disable configuration load from CF card		4 OFF (SysACE Mode = 0) // Disable configuration load from CF card
	3 OFF (SysACE Addr 2 = 0) // Three address bits, ~~0 means the first one(.ace file locates in /XILINX/cfg0/ directory in CF card)~~		3 OFF (SysACE Addr 2 = 0) // Three address bits, don't care here
	2 OFF (SysACE Addr 1 = 0)		2 OFF (SysACE Addr 1 = 0)
	1 OFF (SysACE Addr 0 = 0)		1 OFF (SysACE Addr 0 = 0)

Sya081: Added descriptions of the steps for buring the FPGA configuration files and u-boot/linux images into the on-board flashes.

2012-02-23T16:01:59Z

Added descriptions of the steps for buring the FPGA configuration files and u-boot/linux images into the on-board flashes.

← Older revision		Revision as of 16:01, 23 February 2012
Line 208:		Line 208:

	*For Virtex, there are signals related with the Focal unit and DMA engine, like the current counts of FIFOs, the FIFO status, external and internal(for test) frame_sync/spill_valid signals and so on. Normally it can be triggered with frame_sync, if you want to look know the status of FIFO, you can trigger with the FIFO_full/FIFO_empty or FIFO_count signals.		*For Virtex, there are signals related with the Focal unit and DMA engine, like the current counts of FIFOs, the FIFO status, external and internal(for test) frame_sync/spill_valid signals and so on. Normally it can be triggered with frame_sync, if you want to look know the status of FIFO, you can trigger with the FIFO_full/FIFO_empty or FIFO_count signals.

			==Auto boot the system==

			After the firmware/bootloader/Linux developments are finished, we can burn these files into the on-board flash memories, to make the system boot up automatically after power on. There are three different kinds of flash memories available, a 2GB CF card, a 16MB platform flash and a 32MB BPI linear flash. We can put the FPGA configuration file in CF card or in the platform flash, and the BPI flash is the one for bootloader and Linux image.

			===Program the CF card===
			The CF card supports up to 8 configuration files, which is selected by the S1 switch on the Virtex board. We can generate a new .ace file with iMPACT and overwrite one of the 8 files in CF card, then enable the SysACE CF load and give the correct SysACE address:
			<pre>
			S1:
			4 ON (SysACE Mode = 1) // Enable configuration load from CF card
			3 OFF (SysACE Addr 2 = 0) // Three address bits, 0 means the first one(.ace file locates in /XILINX/cfg0/ directory in CF card)
			2 OFF (SysACE Addr 1 = 0)
			1 OFF (SysACE Addr 0 = 0)
			S2:
			6 OFF (FLASH_A23 = 0)
			5 ON (M2 = 1) // JTAG mode
			4 OFF (M1 = 0)
			3 ON (M0 = 1)
			2 ON (CS_SEL = 1) // Select Linear flash access
			1 OFF (EXT_CCLK = 0)
			</pre>

			===Program the Platform flash===
			The platform flash supports in system programing, we can program it in iMPACT, with the .mcs file also generated in iMPACT. Please refer to [http://www.xilinx.com/support/documentation/user_guides/ug438.pdf Platform Flash XL Configuration and Storage Device]. Switches should be set up as below:
			<pre>
			S1:
			4 OFF (SysACE Mode = 0) // Disable configuration load from CF card
			3 OFF (SysACE Addr 2 = 0) // Three address bits, 0 means the first one(.ace file locates in /XILINX/cfg0/ directory in CF card)
			2 OFF (SysACE Addr 1 = 0)
			1 OFF (SysACE Addr 0 = 0)
			S2:
			6 OFF (FLASH_A23 = 0) // Don't care in this mode
			5 ON (M2 = 1) // Slave SelectMAP mode
			4 ON (M1 = 1)
			3 OFF (M0 = 0)
			2 OFF (CS_SEL = 0) // Select Platform flash access
			1 OFF (EXT_CCLK = 0)
			</pre>
			===Burn bootloader and Linux image===
			This should be done in u-boot prompt window, for bootloader, we need binary file "u-boot-s.bin", which can be find in the petalinux-dist/images/ directory, you need to copy this file together with the linux kernel image "image.ub" to the TFTP server root directory.
			<pre>
			U-Boot-PetaLinux> run update_uboot
			U-Boot-PetaLinux> run update_kernel
			</pre>

	[[Category:Focal]]		[[Category:Focal]]

Sya081 at 13:58, 22 February 2012

2012-02-22T13:58:44Z

← Older revision		Revision as of 13:58, 22 February 2012
Line 56:		Line 56:
	XMD% connect mb mdm -debugdevice devicenr 4		XMD% connect mb mdm -debugdevice devicenr 4
	XMD% dow u-boot.elf		XMD% dow u-boot.elf
			XMD% run
			</pre>

			If there is something wrong, like no response from the console, you can restart the system without reconfiguring Virtex6 FPGA:
			<pre>
			XMD% stop
	XMD% run		XMD% run
	</pre>		</pre>

Sya081 at 15:53, 17 February 2012

2012-02-17T15:53:46Z

← Older revision		Revision as of 15:53, 17 February 2012
Line 166:		Line 166:
	0x1FF // U2_BKUP 9 bits for future use, HEX		0x1FF // U2_BKUP 9 bits for future use, HEX
	</pre>		</pre>
			Notes:
			*Chip_enable: 1=enable;0=disable. LSB = chip 1;
			*Readout_clk_src: b'00=chip1(J10); b'10=chip2(J11); b'01=chip3(J13); b'11=chip4(J12). LSB = Layer 1
			*Frame_sync_src: 0=layer1...5=layer6. Make sure there is a working MK_CLKD signal for the selected layer.
	Slow control parameters will be saved inside Spartan FPGAs, so normally only one time of slow control operation is needed.		Slow control parameters will be saved inside Spartan FPGAs, so normally only one time of slow control operation is needed.