FreeRTOS FSBL - Revision history

Yag005 at 18:23, 6 December 2017

2017-12-06T18:23:32Z

← Older revision		Revision as of 18:23, 6 December 2017
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	Choose "Bootloader" as partition type, and navigate to the file "FSBL.elf" under \axi4_lite_tutorial_project.sdk\FSBL\Debug\ in the file path.<br />		Choose "Bootloader" as partition type, and navigate to the file "FSBL.elf" under \axi4_lite_tutorial_project.sdk\FSBL\Debug\ in the file path.<br />
	Now add a new partition, this time as type "datafile". The file that should be added to file path is "design_1_wrapper.bit" under \axi4_lite_tutorial_project.runs\impl_1\<br />		Now add a new partition, this time as type "datafile". The file that should be added to file path is "design_1_wrapper.bit" under \axi4_lite_tutorial_project.runs\impl_1\<br />
	The third and final partition~~: Partition~~ type "datafile", name: FreeRTOS_example_project.elf ~~File path:~~ \axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\Debug\<br />		The third and final partition is of type "datafile", has the name "FreeRTOS_example_project.elf", and is found at \axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\Debug\<br />
	<br />		<br />
	When all partitions have been added, click "Create Image". Navigate to the directory you specified for output, in our case \axi4_lite_tutorial_project.sdk\output.		When all partitions have been added, click "Create Image". Navigate to the directory you specified for output, in our case \axi4_lite_tutorial_project.sdk\output.

Yag005 at 18:22, 6 December 2017

2017-12-06T18:22:13Z

← Older revision		Revision as of 18:22, 6 December 2017
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	The Project Explorer should now contain the following:		The Project Explorer should now contain the following:
	[[File:fsbl_created.png\|400px\|center]]<br />		[[File:fsbl_created.png\|400px\|center]]<br />

			Goto ''Xilinx --> Create Boot Image''. Choose the Zynq architecture and click to browse for a Output BIF file path. Name the file "output.bif" and create a folder called "output" within the axi4_lite_tutorial_project.sdk directory. Click OK.
			Check that the output format is "BIN". Now click add in the Boot Image Partitions section:

			Choose "Bootloader" as partition type, and navigate to the file "FSBL.elf" under \axi4_lite_tutorial_project.sdk\FSBL\Debug\ in the file path.<br />
			Now add a new partition, this time as type "datafile". The file that should be added to file path is "design_1_wrapper.bit" under \axi4_lite_tutorial_project.runs\impl_1\<br />
			The third and final partition: Partition type "datafile", name: FreeRTOS_example_project.elf File path: \axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\Debug\<br />
			<br />
			When all partitions have been added, click "Create Image". Navigate to the directory you specified for output, in our case \axi4_lite_tutorial_project.sdk\output.
			It should now contain two files: BOOT.bin, and output.bif. Copy the BOOT.bin file onto an SD-card formatted as FAT.

			Bring up your favorite Xilinx Zybo SoC board, and configure jumper 5 (JP5) for SD boot configuration. Insert the SD card, and connect a power source (wall or USB). Then power up the board. After a couple of seconds, it should behave just as it did when booting from JTAG in the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

Yag005 at 17:53, 6 December 2017

2017-12-06T17:53:43Z

← Older revision		Revision as of 17:53, 6 December 2017
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	Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.		Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.


	This tutorial assumes you have completed the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.		This tutorial assumes you have completed the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.


	===== ~~Exporting hardware bitstream~~ =====		===== Creating FSBL =====

	~~After the bitstream was generated in the previous tutorial, it is now possible to export it.~~
	~~''Goto: File -> Export -> Export Hardware..''~~
	~~Make sure to include bitstream, and press "OK".~~
	~~[[File:export_hardware.png\|thumbnail\|center]]~~


	~~Next~~, ~~goto: ''File -> Launch SDK''. The following window will appear~~:		The result from the previous tutorial linked at the top of this tutorial, should be a Project Explorer looking like this:
	[[File:~~Launch SDK~~.png\|~~thumbnail~~\|center]]		[[File:project_explorer_start.png\|400px\|center]]<br />
	~~Press "OK" and wait for Xilinx SDK to start up and finish loading.~~

	... ~~Work in progress .~~..		Goto ''File --> New --> Application Project''. Name the new project "FSBL" and let OS platform be "standalone". On the next page, choose the "Zynq FSBL"-template. Finish.
			The Project Explorer should now contain the following:
			[[File:fsbl_created.png\|400px\|center]]<br />

Yag005 at 12:25, 6 December 2017

2017-12-06T12:25:05Z

← Older revision		Revision as of 12:25, 6 December 2017
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	This tutorial assumes you have completed the "[[~~Creating example project with AXI4 Lite peripheral in~~ Xilinx ~~Vivado~~]]"-tutorial.		This tutorial assumes you have completed the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

Yag005 at 13:50, 28 November 2017

2017-11-28T13:50:04Z

← Older revision		Revision as of 13:50, 28 November 2017
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	Next, goto: ''File -> Launch SDK''. The following window will appear:		Next, goto: ''File -> Launch SDK''. The following window will appear:
	[[File:Launch SDK.png\|thumbnail\|center]]		[[File:Launch SDK.png\|thumbnail\|center]]
	Press "OK".		Press "OK" and wait for Xilinx SDK to start up and finish loading.

			... Work in progress ...

Yag005 at 13:46, 28 November 2017

2017-11-28T13:46:46Z

← Older revision		Revision as of 13:46, 28 November 2017
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	''Goto: File -> Export -> Export Hardware..''		''Goto: File -> Export -> Export Hardware..''
	Make sure to include bitstream, and press "OK".		Make sure to include bitstream, and press "OK".
	[[File:export_hardware.png\|~~400px~~\|center]]		[[File:export_hardware.png\|thumbnail\|center]]

Yag005 at 13:46, 28 November 2017

2017-11-28T13:46:30Z

← Older revision		Revision as of 13:46, 28 November 2017
Line 9:		Line 9:
	After the bitstream was generated in the previous tutorial, it is now possible to export it.		After the bitstream was generated in the previous tutorial, it is now possible to export it.
	''Goto: File -> Export -> Export Hardware..''		''Goto: File -> Export -> Export Hardware..''
	~~Click~~ to include bitstream, and press "OK".		Make sure to include bitstream, and press "OK".
			[[File:export_hardware.png\|400px\|center]]


	Next, goto: ''File -> Launch SDK''. The following window will appear:		Next, goto: ''File -> Launch SDK''. The following window will appear:
	[[File:Launch SDK.png\|thumbnail\|center]]		[[File:Launch SDK.png\|thumbnail\|center]]
	Press "OK".		Press "OK".

Yag005 at 13:44, 28 November 2017

2017-11-28T13:44:20Z

← Older revision		Revision as of 13:44, 28 November 2017
Line 12:		Line 12:

	Next, goto: ''File -> Launch SDK''. The following window will appear:		Next, goto: ''File -> Launch SDK''. The following window will appear:
	[[File:Launch SDK.png\|thumbnail]]		[[File:Launch SDK.png\|thumbnail\|center]]
	Press "OK".		Press "OK".

Yag005 at 13:42, 28 November 2017

2017-11-28T13:42:01Z

← Older revision		Revision as of 13:42, 28 November 2017
Line 1:		Line 1:
	Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.		Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.


	This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.		This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.


	===== Exporting hardware bitstream =====		===== Exporting hardware bitstream =====

			After the bitstream was generated in the previous tutorial, it is now possible to export it.
			''Goto: File -> Export -> Export Hardware..''
			Click to include bitstream, and press "OK".

			Next, goto: ''File -> Launch SDK''. The following window will appear:
			[[File:Launch SDK.png\|thumbnail]]
			Press "OK".

Yag005: Created page with "Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS. This tutorial assumes you have completed the "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"-t..."

2017-11-28T13:33:45Z

Created page with "Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS. This tutorial assumes you have completed the "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"-t..."

New page

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.

This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

===== Exporting hardware bitstream =====