FOCAL - Forward Calorimeter - Revision history

Dfe002 at 14:47, 10 August 2012

2012-08-10T14:47:13Z

← Older revision		Revision as of 14:47, 10 August 2012
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	* [[Programming Mimosa chips]]		* [[Programming Mimosa chips]]

	* [[~~Readout software~~]]		==Readout software==
			[[Report by Tony]]

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]

Dfe002 at 14:46, 10 August 2012

2012-08-10T14:46:19Z

← Older revision		Revision as of 14:46, 10 August 2012
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	* [[Programming Mimosa chips]]		* [[Programming Mimosa chips]]

	~~== Shopping list ==~~		* [[Readout software]]

	~~1x 2U 335mm Rack mount enclosure, Grey - 665-7712 - 556,29<br>~~
	~~1x RD-125A Switch Mode PSU, 5V/15A,12V/10A - 644-6941 - 662,16<br>~~
	~~3x DC/DC PoL,DOSA,2.4-5.5Vin,0.75-3.3Vo 6A - 150-758 - 116,16<br>~~
	~~1x 4.20mm,housing,MiniFit,receptacle,DR,6w, - 679-5773 - 2,064<br>~~
	~~http://www.samtec.com/search/vita57fmc.aspx<br>~~
	~~1x BULGIN - BZH01/Z0000/11 - INLET, IEC, SWITCHED, RED - F9997237 - 57,39<br>~~
	~~1x MH CONNECTORS - MH3101S-8821 - COUPLER, RJ45, SHIELDED - F1122292 - 92,11<br>~~
	~~12x TYCO ELECTRONICS / AMP - 5569262-1 - JACK, RJ45, MULTI PORT, 2X4 - F1162485 - 102,42<br>~~
	~~2x L-COM - ECF504B-UAB - Modular Coupler - F1702375 - 91,31<br>~~
	~~2x USB cables - F1076669 - F1308878~~

	[[Category:Mikroelektronikk]]		[[Category:Mikroelektronikk]]

Sya081 at 16:36, 23 February 2012

2012-02-23T16:36:34Z

← Older revision		Revision as of 16:36, 23 February 2012
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	==== Software ====		==== Software ====
	~~The software driver for the message buffer system can be found here:~~		* [[Setting Up PetaLinux System]]
	~~http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-dcs/trunk/rculinux/dcscMsgBufferInterface/~~

	[~~[Setting Up PetaLinux System]~~]		* Petalinux documentation: [http://www.petalogix.com/resources/documentation/petalinux_sdk petalinux_sdk]

	~~Petalinux documentation:~~		* [[Get readout box up and running]]
	[~~http://www.petalogix.com/resources/documentation/petalinux_sdk petalinux_sdk~~]

	[[~~Get readout box up and running]]~~		* [[Programming Mimosa chips]]

	~~== Download section ==~~
	~~#[[Media:svf_specification.pdf\|Serial Vector Format(SVF) Specification]]~~
	~~#[[Media:svf_xilinx.pdf\|SVF and XSVF File Formats for Xilinx Devices~~]]

	== Shopping list ==		== Shopping list ==

Sya081 at 16:24, 23 February 2012

2012-02-23T16:24:41Z

← Older revision		Revision as of 16:24, 23 February 2012
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	Petalinux documentation:		Petalinux documentation:
	[http://www.petalogix.com/resources/documentation/petalinux_sdk]		[http://www.petalogix.com/resources/documentation/petalinux_sdk petalinux_sdk]

	[[Get readout box up and running]]		[[Get readout box up and running]]

Dfe002: /* Software */

2012-01-18T07:51:36Z

Software

← Older revision		Revision as of 07:51, 18 January 2012
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	Petalinux documentation:		Petalinux documentation:
	[http://www.petalogix.com/resources/documentation/petalinux_sdk]		[http://www.petalogix.com/resources/documentation/petalinux_sdk]

			[[Get readout box up and running]]

	== Download section ==		== Download section ==

Lbr088 at 09:28, 15 June 2011

2011-06-15T09:28:15Z

← Older revision		Revision as of 09:28, 15 June 2011
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	http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-dcs/trunk/rculinux/dcscMsgBufferInterface/		http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-dcs/trunk/rculinux/dcscMsgBufferInterface/

	[[~~Setting_Up_PetaLinux_System~~]]		[[Setting Up PetaLinux System]]

	Petalinux documentation:		Petalinux documentation:

Lbr088 at 09:27, 15 June 2011

2011-06-15T09:27:14Z

← Older revision		Revision as of 09:27, 15 June 2011
Line 28:		Line 28:
	The software driver for the message buffer system can be found here:		The software driver for the message buffer system can be found here:
	http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-dcs/trunk/rculinux/dcscMsgBufferInterface/		http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/alice-dcs/trunk/rculinux/dcscMsgBufferInterface/

			[[Setting_Up_PetaLinux_System]]

	Petalinux documentation:		Petalinux documentation:
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	2x L-COM - ECF504B-UAB - Modular Coupler - F1702375 - 91,31<br>		2x L-COM - ECF504B-UAB - Modular Coupler - F1702375 - 91,31<br>
	2x USB cables - F1076669 - F1308878		2x USB cables - F1076669 - F1308878

			[[Category:Mikroelektronikk]]

Sya081 at 13:23, 12 May 2011

2011-05-12T13:23:19Z

← Older revision		Revision as of 13:23, 12 May 2011
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	== Mimosa chips ==		== Mimosa chips ==
	* [[Media:PH1-UserMan-20080916.pdf\|preliminary user manual of Phase1]]		* [[Media:PH1-UserMan-20080916.pdf\|preliminary user manual of Phase1]]
	* [[Media:mimosa.bsd.txt\|BSDL file of Phase1]], which can be used for JTAG test, such as an XJTAG module.		* [[Media:mimosa.bsd.txt\|BSDL file of Phase1]], which can be used for JTAG test, such as with an XJTAG module.
	* [[Media:pattern_test.svf.txt\|SVF file for pattern-only mode test of Phase1]], Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.		* [[Media:pattern_test.svf.txt\|SVF file for pattern-only mode test of Phase1]], Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.

Sya081 at 13:05, 12 May 2011

2011-05-12T13:05:57Z

← Older revision		Revision as of 13:05, 12 May 2011
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	* Spartan6 FPGA type: [http://www.xilinx.com/support/documentation/spartan-6.htm XC6SLX150-FGG676, speed-grade: 3]		* Spartan6 FPGA type: [http://www.xilinx.com/support/documentation/spartan-6.htm XC6SLX150-FGG676, speed-grade: 3]
	* Examples of user constraint files for Spartan6 FPGAs: [[Media:U1.ucf.txt\| U1 ]],[[Media:U2.ucf.txt\| U2 ]]		* Examples of user constraint files for Spartan6 FPGAs: [[Media:U1.ucf.txt\| U1 ]],[[Media:U2.ucf.txt\| U2 ]]
	* EXamples of VHDL entity definations for Spartan6 FPGAs: [[Media:U1.vhdl.txt\| U1 ]],[[Media:U2.vhdl.txt\| U2 ]		* EXamples of VHDL entity definations for Spartan6 FPGAs: [[Media:U1.vhdl.txt\| U1 ]],[[Media:U2.vhdl.txt\| U2 ]]

	=== Control and Readout board ===		=== Control and Readout board ===

Sya081 at 13:05, 12 May 2011

2011-05-12T13:05:22Z

← Older revision		Revision as of 13:05, 12 May 2011
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	from the Mimosa chips to the readout electronics.		from the Mimosa chips to the readout electronics.
	== Overview ==		== Overview ==
			[[Media:Focal readout.pdf\|Simple description of the Alice Focal readout electronics]].

	== Mimosa chips ==		== Mimosa chips ==
	* [[Media:PH1-UserMan-20080916.pdf\|preliminary user manual of Phase1]]		* [[Media:PH1-UserMan-20080916.pdf\|preliminary user manual of Phase1]]
	* [[Media:mimosa.bsd.txt\|BSDL file of Phase1]]		* [[Media:mimosa.bsd.txt\|BSDL file of Phase1]], which can be used for JTAG test, such as an XJTAG module.
			* [[Media:pattern_test.svf.txt\|SVF file for pattern-only mode test of Phase1]], Use XJTAG to configure Phase1 chip with it, LVDS data output signals will appear on the 4 channels after supplying 160MHz differential clock and START signal.

	== Readout electronics ==		== Readout electronics ==

	=== Adapterboard /Fanoutboard ===		=== Adapterboard /Fanoutboard ===
	The adapterboard and fan-out boards provide LVDS interfaces and JTAG interfaces between the Control and Read-out board and the Mimosa ASICs. Here is [[Media:Focal_read-out_board_schematics.pdf\|the schematics of the boards]].		The adapterboard and fan-out boards provide LVDS interfaces and JTAG interfaces between the Control and Read-out board and the Mimosa ASICs. Here is [[Media:Focal_read-out_board_schematics.pdf\|the schematics of the boards]].
			* Spartan6 FPGA type: [http://www.xilinx.com/support/documentation/spartan-6.htm XC6SLX150-FGG676, speed-grade: 3]
			* Examples of user constraint files for Spartan6 FPGAs: [[Media:U1.ucf.txt\| U1 ]],[[Media:U2.ucf.txt\| U2 ]]
			* EXamples of VHDL entity definations for Spartan6 FPGAs: [[Media:U1.vhdl.txt\| U1 ]],[[Media:U2.vhdl.txt\| U2 ]

	=== Control and Readout board ===		=== Control and Readout board ===
	The idea is to use a [http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm Xilinx Virtex 6 development board] as a first prototype. The board will run Petalinux, and some software to access the firmware registers. A software framework for the TPC detector is to be adapted for the use on the Virtex 6 board and Petalinux.		The idea is to use a [http://www.xilinx.com/products/devkits/EK-V6-ML605-G.htm Xilinx Virtex 6 development board] as a first prototype. The board will run Petalinux, and some software to access the firmware registers. A software framework for the TPC detector is to be adapted for the use on the Virtex 6 board and Petalinux.
			*[[Media:ML605.ucf.txt\|FPGA user constraint file for Virtex 6 development board]]

	==== Firmware ====		==== Firmware ====
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	== Download section ==		== Download section ==
			#[[Media:svf_specification.pdf\|Serial Vector Format(SVF) Specification]]
			#[[Media:svf_xilinx.pdf\|SVF and XSVF File Formats for Xilinx Devices]]

	== Shopping list ==		== Shopping list ==