CZT-firmware - Revision history

Ako054: /* LED control */

2010-10-18T19:10:44Z

LED control

← Older revision		Revision as of 19:10, 18 October 2010
Line 110:		Line 110:
	==RCU master (rcumaster)==		==RCU master (rcumaster)==
	===LED control===		===LED control===
			FSM

	===Memory bus interface (mb_if)===		===Memory bus interface (mb_if)===
	see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in detector module interface		see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in detector module interface

2010-10-18T19:08:23Z

Timetag generation (tt_gen)

← Older revision		Revision as of 19:08, 18 October 2010
Line 133:		Line 133:

	==Timetag generation (tt_gen)==		==Timetag generation (tt_gen)==
			The time tag generator provides information about when an event happens. It maintains a 20-bit counter used to timestamp science events. The 20-bit time stamp then become part of the science data package (SCDP) .

2010-10-18T19:08:08Z

Clock reset (clkrst)

← Older revision		Revision as of 19:08, 18 October 2010
Line 129:		Line 129:

	==Clock reset (clkrst)==		==Clock reset (clkrst)==
			This module generates the clock and the reset signal for the firmware components.
			The signals are based on a crystal oscillator input and a global clock.

	==Timetag generation (tt_gen)==		==Timetag generation (tt_gen)==

2010-10-18T19:07:48Z

Resync register

← Older revision		Revision as of 19:07, 18 October 2010
Line 126:		Line 126:

	==Resync register==		==Resync register==
			synchronizes the inputs and outputs of the FPGA with the internal clock signal.

	==Clock reset (clkrst)==		==Clock reset (clkrst)==
	==Timetag generation (tt_gen)==		==Timetag generation (tt_gen)==

2010-10-18T19:05:48Z

Address decoder (adrdec_bgo)

← Older revision		Revision as of 19:05, 18 October 2010
Line 81:		Line 81:
	* delivers answer (memdat, memory data) from modules		* delivers answer (memdat, memory data) from modules

			'''modules in control/status chain:'''
			* detector module interfaces (4 -- one per chain)
			* XA configuration (4 -- one per chain)
			* RCU master
			* bin control

	'''input: '''		'''input: '''
	* memadr_in (from dpu_if/user)		* memadr_in (from dpu_if/user)
	* memdat_out_[0-4] (from modules)		* memdat_out_[0-9] (from modules)
	* clk etc.		* clk etc.

2010-10-18T18:58:43Z

Memory bus interface

← Older revision		Revision as of 18:58, 18 October 2010
Line 115:		Line 115:
	RAM to memorize control register, dual port RAM for volatile XA configuration data		RAM to memorize control register, dual port RAM for volatile XA configuration data
	===Memory bus interface===		===Memory bus interface===
			see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in detector module interface

	===piso8_ctrl===		===piso8_ctrl===
	FSM		FSM

2010-10-18T18:58:36Z

Memory bus interface (mb_if)

← Older revision		Revision as of 18:58, 18 October 2010
Line 106:		Line 106:
	===LED control===		===LED control===
	===Memory bus interface (mb_if)===		===Memory bus interface (mb_if)===
			see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in detector module interface

	==XA config (xa_cfg)==		==XA config (xa_cfg)==

2010-10-18T18:57:26Z

MUX (scdp_ch_mux)

← Older revision		Revision as of 18:57, 18 October 2010
Line 28:		Line 28:

	==MUX (scdp_ch_mux)==		==MUX (scdp_ch_mux)==
			The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

	==FIFO==		==FIFO==
	==DPU interface (dpu_if) ==		==DPU interface (dpu_if) ==

2010-10-18T18:54:21Z

Binning control module (BCM) (bin_ctrl_module)

← Older revision		Revision as of 18:54, 18 October 2010
Line 90:		Line 90:

	==Binning control module (BCM) (bin_ctrl_module) ==		==Binning control module (BCM) (bin_ctrl_module) ==
			The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
			There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

	===Scdp channel mux===		===Scdp channel mux===
	===Bin address generator===		===Bin address generator===
Line 96:		Line 99:
	===Bin module address arbiter===		===Bin module address arbiter===
	===Memory bus interface (mb_if)===		===Memory bus interface (mb_if)===
			see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in detector module interface

	==RCU master (rcumaster)==		==RCU master (rcumaster)==
	===LED control===		===LED control===

2010-10-18T18:52:33Z

Address decoder (adrdec_bgo)

← Older revision		Revision as of 18:52, 18 October 2010
Line 75:		Line 75:
	memory bus address decoder and data multiplexor		memory bus address decoder and data multiplexor

	* decodes the memory_address_in (memadr_in) and delivers data to called modules ~~(pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)~~		* decodes the memory_address_in (memadr_in) and delivers data to called modules
	* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.		* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
	* delivers answer (memdat, memory data) from modules		* delivers answer (memdat, memory data) from modules