Busy Box and related/BusyBox Registers - Revision history

Nfyku at 07:37, 24 April 2012

2012-04-24T07:37:45Z

2012-04-24T07:15:18Z

2012-04-24T06:44:06Z

Updated Trigger Modules Regesiter definition

2012-04-23T13:20:43Z

← Older revision		Revision as of 13:20, 23 April 2012
Line 237:		Line 237:
	\|rowspan="11"\|Control		\|rowspan="11"\|Control
	\|rowspan="11"\|0x3000		\|rowspan="11"\|0x3000
	\|RW		\|RW
	\|[~~15:13~~]		\|[0]
	\|~~Unused~~		\|Serial B channel on/off Default: 1
	\|----		\|----
	\|RW		\|RW
	\|[12]		\|[1]
	\|~~Trigger Input Mask Enable. Default=~~0		\|Disable_error_masking 0
	\|----		\|----
	\|RW		\|RW
	\|[11]		\|[2]
	\|~~L1a message mask. Default=1~~		\|NA 0
	\|----		\|----
	\|RW		\|RW
	\|[10]		\|[3]
	\|~~L2 Timeout FIFO storage mask. Default=~~1		\|L0 support 1
	\|----		\|----
	\|RW		\|RW
	\|[9]		\|[4:7]
	\|~~L2r FIFO storage mask. Default=1~~		\|Not Used
	\|----		\|----
	\|RW		\|RW
	\|[8]		\|[8]
	\|L2a FIFO storage mask~~. Default=~~1		\|L2a FIFO storage mask 1
	\|----		\|----
	\|RW		\|RW
	\|[~~7:4~~]		\|[9]
	\|~~Unused~~		\|L2r FIFO storage mask 1
	\|----		\|----
	\|RW		\|RW
	\|[3]		\|[10]
	\|~~L0 support. Default=~~1		\|L2 Timeout FIFO storage mask 1
	\|----		\|----
	\|RW		\|RW
	\|[2]		\|[11]
	\|~~Enable RoI decoding. Default=0~~		\|L1a message mask 1
	\|----		\|----
	\|RW		\|RW
	\|[1]		\|[12]
	\|~~Disable_error_masking. Default=~~0		\|Trigger Input Mask Enable 0
	\|----		\|----
	\|RW		\|RW
	\|[0]		\|[13:15]
	\|~~Serial B channel on/off. Default=1~~		\|Not Used
	\|----		\|----
	\|~~rowspan="6"\|Control~~		\|RW
	~~\|rowspan="6"\|0x3001~~		\|[16]
	\|R		\|Bunch_counter overflow
	\|[~~15:8~~]
	\|~~Trigger Receiver Version. Default=0x13~~
	\|----		\|----
	\|R		\|RW
	\|[~~7:4~~]		\|[17]
	\|~~CDH version. Default=0x2~~		\|Run Active -
	\|----		\|----
	\|R		\|RW
	\|[3]		\|[18]
	~~\|Not Used~~
	~~\|----~~
	\|R
	~~\|[2]~~
	\|Busy (receiving sequence) -		\|Busy (receiving sequence) -
	\|----		\|----
	\|R		\|RW
	\|[1]		\|[19]
	\|~~Run Active -~~		\|Not Used
	\|----		\|----
	\|R		\|RW
	\|[0]		\|[23:20]
	\|~~Bunch_counter overflow -~~		\|CDH version 0x2
	\|----		\|----
	\|Module Reset		\|Module Reset

2011-08-12T12:56:41Z

Changed from L0 to L1A trigger timeout

← Older revision		Revision as of 12:56, 12 August 2011
Line 70:		Line 70:
	\|0x0000		\|0x0000
	\|-		\|-
	\|L0 Trigger Timeout(15:0)		\|L1 Trigger Timeout(15:0)
	\|0x2008		\|0x2008
	\|RW		\|RW
	\|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.		\|Time in 10 us resolution the 'busy' will be asserted after an L1A trigger. Note: The busy will not be deasserted if the buffers are full.
	\|0x000A		\|0x000A
	\|-		\|-
Line 82:		Line 82:
	* Bit 15 - Busy because TTCrx_ready is low.		* Bit 15 - Busy because TTCrx_ready is low.
	* Bit 14 - Busy because MEB count >= MEB limit		* Bit 14 - Busy because MEB count >= MEB limit
	* Bit 13 - Busy because L0 timeout is active.		* Bit 13 - Busy because L1 timeout is active.
	* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.		* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
	* Bit 11 - Busy because the maximum Trigger Burst length has been exceeded.		* Bit 11 - Busy because the maximum Trigger Burst length has been exceeded.

2010-08-18T13:50:50Z

Corrected L1_msg_latency register addresses

2010-08-18T13:47:08Z

Corrected addresses for Event info and Event Error

2010-08-10T11:34:50Z

← Older revision		Revision as of 11:34, 10 August 2010
Line 149:		Line 149:
	\|0x2015		\|0x2015
	\|R		\|R
	\|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 53		\|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 54
	\|~~0x0022~~		\|0x0036
	\|-		\|-
	\|Stresstest Enable(0)		\|Stresstest Enable(0)

2010-06-29T07:57:02Z

Updated current version to 53

← Older revision		Revision as of 07:57, 29 June 2010
Line 149:		Line 149:
	\|0x2015		\|0x2015
	\|R		\|R
	\|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 48		\|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 53
	\|0x0022		\|0x0022
	\|-		\|-

2010-06-02T09:07:15Z

Added the new Trigger Mode register. Updated status register info.

← Older revision		Revision as of 09:07, 2 June 2010
Line 85:		Line 85:
	* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.		* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
	* Bit 11 - Busy because the maximum Trigger Burst length has been exceeded.		* Bit 11 - Busy because the maximum Trigger Burst length has been exceeded.
	* Bit 10:8 - Unused		* Bit 10 - Busy because two buffers are, or have been used, in new sparse mode
			* Bit 9:8 - Unused
	* Bit 7:4 - Current MEB count.		* Bit 7:4 - Current MEB count.
	* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.		* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
Line 167:		Line 168:
	\|RW		\|RW
	\|Leak time for the Burst Interlock "leaky bucket" defined in steps of 10 us. Maximum leak time is 655.4 ms.		\|Leak time for the Burst Interlock "leaky bucket" defined in steps of 10 us. Maximum leak time is 655.4 ms.
			\|0x0000
			\|-
			\|Trigger Mode(2:0)
			\|0x2019
			\|RW
			\|Control registers concerning the BUSY/trigger mode
			* Bit 2 - Not used
			* Bit 1 - New sparse mode enabled
			* Bit 0 - Not used
	\|0x0000		\|0x0000
	\|-		\|-