Busy Box and related - Revision history

Nfyku: Updated to version 66

2016-06-07T11:35:47Z

Updated to version 66

← Older revision		Revision as of 11:35, 7 June 2016
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	*[http://subversion.ift.uib.no/svn/busybox_firmware BusyBox SVN repository]		*[http://subversion.ift.uib.no/svn/busybox_firmware BusyBox SVN repository]
	*[~~http~~://~~web~~.~~ift~~.~~uib.no~~/~~kjekscgi~~-~~bin~~/~~viewcvs.cgi~~/~~vhdlcvs~~/~~trigger_receiver~~/ Trigger Receiver ~~CVS~~]		*[https://gitlab.cern.ch/alice-tpc-rcu2/GIT-ALICE-RCU2/tree/ttc/RCU2/firmware/SF2/src/modules/ttcrx Trigger Receiver GIT repos]


	====BusyBox FPGAs====		====BusyBox FPGAs====

	There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. ~~Alternatively fpga2 can be prgrammed~~ with '~~dummy~~.bit'.		There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. From version 65 only one FPGA is in use. Make sure to program the second FPGA with 'fpga2_dummy.bit', else the FPGAs can not be accessed from the DCS card.


	==== Compiled BusyBox Firmware Versions ====		==== Compiled BusyBox Firmware Versions ====

	~~=====Revision 31=====~~
	~~;:* Using Trigger Receiver Module v.1.3~~
	~~;:* Now handles orphan L2 Accept triggers by looking at the payload bit in the event info.~~
	~~;:;Download~~
	~~;::*[http://web.ift.uib.no/firmware/BusyBox/revision31/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]~~
	~~;::*[http://web.ift.uib.no/firmware/BusyBox/revision31/busybox_fpga1.bit busybox_fpga1.bit]~~
	~~;::*[http://web.ift.uib.no/firmware/BusyBox/revision31/busybox_fpga2.bit busybox_fpga2.bit]~~

	======Versioning======		======Versioning======
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	======Download======		======Download======
	*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1.bit busybox_fpga1.bit]		*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1.bit busybox_fpga1.bit]
			*[http://web.ift.uib.no/firmware/BusyBox/fpga2_dummy.bit fpga2_dummy.bit]

	=====Revision 66=====		=====Revision 66=====
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	======Download======		======Download======
	*[http://web.ift.uib.no/firmware/BusyBox/revision66/busybox_fpga1.bit busybox_fpga1.bit]		*[http://web.ift.uib.no/firmware/BusyBox/revision66/busybox_fpga1.bit busybox_fpga1.bit]
			*[http://web.ift.uib.no/firmware/BusyBox/fpga2_dummy.bit fpga2_dummy.bit]

	==== DCS board firmware for BusyBox ====		==== DCS board firmware for BusyBox ====

Are033 at 07:05, 7 June 2016

2016-06-07T07:05:13Z

← Older revision		Revision as of 07:05, 7 June 2016
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	Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.		Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.

	The BusyBoxes are located in the DAQ counting ~~rom~~.		The BusyBoxes are located in the DAQ counting room.

	== BusyBox Hardware overview ==		== BusyBox Hardware overview ==
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	*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1.bit busybox_fpga1.bit]		*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1.bit busybox_fpga1.bit]

			=====Revision 66=====
			======Using Trigger Receiver Module v 2.1 (06.06.2016)======
			[https://twiki.cern.ch/twiki/bin/viewauth/ALICE/TPC_RCU2_TTC_Module Click for Trigger Receiver updates]

			*This release only updates the trigger receiver module and firmware is tested to receive all valid trigger sequences.
			*Please perform a complete integration (DAQ+RCU+BusyBox) test in lab before using it at experiment.

			This BusyBox firmware version has been compiled with ISE version 13.2

			======Download======
			*[http://web.ift.uib.no/firmware/BusyBox/revision66/busybox_fpga1.bit busybox_fpga1.bit]

	==== DCS board firmware for BusyBox ====		==== DCS board firmware for BusyBox ====

Are033: /* Using Trigger Receiver Module v 1.9 (30.06.2015) */

2016-05-19T18:02:31Z

Using Trigger Receiver Module v 1.9 (30.06.2015)

← Older revision		Revision as of 18:02, 19 May 2016
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	======Using Trigger Receiver Module v 1.9 (30.06.2015)======		======Using Trigger Receiver Module v 1.9 (30.06.2015)======
	* New trigger classes with additional words for Alice CDH version 3		* New trigger classes with additional words for Alice CDH version 3
			* Register map is set according to RCU2:'''Old trigger address map is not valid'''. New address map is found here[[:File:TTCrx_receiver_v2.0.2.pdf]].
	* Reduced number of links on Busy box to comply with new DAQ architect (40 Links). TPC has 36 links (18x2=36), 4 additional links are kept for EMCAL.		* Reduced number of links on Busy box to comply with new DAQ architect (40 Links). TPC has 36 links (18x2=36), 4 additional links are kept for EMCAL.
	* There is only one FPGA needed to work so FPGA1 will be programmed.		* There is only one FPGA needed to work so FPGA1 will be programmed.

Are033: /* Logical address mapping to physical connectors on busy-box */

2016-05-09T12:49:30Z

Logical address mapping to physical connectors on busy-box

← Older revision		Revision as of 12:49, 9 May 2016
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	======Logical address mapping to physical connectors on busy-box======		======Logical address mapping to physical connectors on busy-box======
	* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.		* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.
			[[File:Bb_mapping.jpg]]

	0x2100:DL1		0x2100:DL1
	0x2101:DL2		0x2101:DL2

Are033: /* Logical address mapping to physical connectors on busy-box */

2016-05-09T12:45:18Z

Logical address mapping to physical connectors on busy-box

← Older revision		Revision as of 12:45, 9 May 2016
Line 190:		Line 190:
	======Logical address mapping to physical connectors on busy-box======		======Logical address mapping to physical connectors on busy-box======
	* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.		* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.
	~~[[File:Bb mapping.jpg\|framed\|center\|bb_mapping.jpg]]~~
	0x2100:DL1		0x2100:DL1
	0x2101:DL2		0x2101:DL2

Are033: /* Logical address mapping to physical connectors on busy-box */

2016-05-09T12:41:10Z

Logical address mapping to physical connectors on busy-box

← Older revision		Revision as of 12:41, 9 May 2016
Line 190:		Line 190:
	======Logical address mapping to physical connectors on busy-box======		======Logical address mapping to physical connectors on busy-box======
	* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.		* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.
			[[File:Bb mapping.jpg\|framed\|center\|bb_mapping.jpg]]
	0x2100:DL1		0x2100:DL1
	0x2101:DL2		0x2101:DL2

Are033 at 11:00, 9 May 2016

2016-05-09T11:00:12Z

← Older revision		Revision as of 11:00, 9 May 2016
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	======Logical address mapping to physical connectors on busy-box======		======Logical address mapping to physical connectors on busy-box======
	* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): ~~I counted~~ D: Down, U: Up, L: Left.		* Reference point is GREEN LIGHT on connector side of the busy box (set at LEFT): D: Down, U: Up, L: Left.

	0x2100:DL1		0x2100:DL1

Are033 at 09:43, 9 May 2016

2016-05-09T09:43:39Z

@@ Line 187: / Line 187: @@
 * There is only one FPGA needed to work so FPGA1 will be programmed.
 * -- Hardware note: In this release busy signal from FPGA2 is not used and related I/Os are disabled in Xilinx constraint file.
 This BusyBox firmware version has been compiled with ISE version 13.2

Are033 at 09:12, 22 April 2016

2016-04-22T09:12:57Z

← Older revision		Revision as of 09:12, 22 April 2016
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	* New trigger classes with additional words for Alice CDH version 3		* New trigger classes with additional words for Alice CDH version 3
	* Reduced number of links on Busy box to comply with new DAQ architect (40 Links). TPC has 36 links (18x2=36), 4 additional links are kept for EMCAL.		* Reduced number of links on Busy box to comply with new DAQ architect (40 Links). TPC has 36 links (18x2=36), 4 additional links are kept for EMCAL.
			* There is only one FPGA needed to work so FPGA1 will be programmed.
	* -- Hardware note: In this release busy signal from FPGA2 is not used and related I/Os are disabled in Xilinx constraint file.		* -- Hardware note: In this release busy signal from FPGA2 is not used and related I/Os are disabled in Xilinx constraint file.

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	======Download======		======Download======
	*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]
	*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1.bit busybox_fpga1.bit]		*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga1.bit busybox_fpga1.bit]
	*[http://web.ift.uib.no/firmware/BusyBox/revision65/busybox_fpga2.bit busybox_fpga2.bit]

	==== DCS board firmware for BusyBox ====		==== DCS board firmware for BusyBox ====

Are033 at 07:10, 21 April 2016

2016-04-21T07:10:06Z

@@ Line 180: / Line 180: @@
 *[http://web.ift.uib.no/firmware/BusyBox/revision63/busybox_fpga1.bit busybox_fpga1.bit]
 *[http://web.ift.uib.no/firmware/BusyBox/revision63/busybox_fpga2.bit busybox_fpga2.bit]
 ==== DCS board firmware for BusyBox ====