Bitvis UVVM VHDL Verification Component Framework - Revision history

Nfyku at 12:45, 16 March 2026

2026-03-16T12:45:25Z

← Older revision		Revision as of 12:45, 16 March 2026
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	This wiki page is heavily based on the Powerpoint-presentation found [https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/Simple_TB_step_by_step.pps here].~~<ref>~~		This wiki page is heavily based on the Powerpoint-presentation found [https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/Simple_TB_step_by_step.pps here].

	Copyright 2025 UVVM		Copyright 2025 UVVM
	Licensed under the [http://www.apache.org/licenses/LICENSE-2.0 Apache License, Version 2.0 (the “License”)]		Licensed under the [http://www.apache.org/licenses/LICENSE-2.0 Apache License, Version 2.0 (the “License”)].

	== Introduction ==		== Introduction ==

Nfyku: Updated some external references. Updated from Bitvis to UVVM framework

2026-03-16T12:38:12Z

Updated some external references. Updated from Bitvis to UVVM framework

← Older revision		Revision as of 12:38, 16 March 2026
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	This wiki page is heavily based on the Powerpoint-presentation found [~~http~~://~~bitvis~~.no/~~media~~/~~15298~~/Simple_TB_step_by_step.pps here].<ref>~~UVVM LICENSE AGREEMENT~~		This wiki page is heavily based on the Powerpoint-presentation found [https://github.com/UVVM/UVVM/blob/master/uvvm_util/doc/Simple_TB_step_by_step.pps here].<ref>
	~~IMPORTANT - READ BEFORE USING OR COPYING.~~
	~~THIS IS THE MIT LICENSE, see https://opensource.org/licenses/MIT~~
	~~------------------------------------------------------------------~~

	Copyright ~~(c) 2016 by Bitvis AS~~		Copyright 2025 UVVM
			Licensed under the [http://www.apache.org/licenses/LICENSE-2.0 Apache License, Version 2.0 (the “License”)]
	~~Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated~~
	~~documentation files (~~the ~~"Software"), to deal in the Software without restriction, including without limitation~~
	~~the rights to use, copy, modify, merge, publish, distribute, sublicense, and~~/~~or sell copies of the Software,~~
	~~and to permit persons to whom the Software is furnished to do so, subject to the following conditions:~~

	~~The above copyright notice and this permission notice shall be included in all copies or substantial portions of~~
	~~the Software~~.

	~~THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE~~
	~~WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT~~. ~~IN NO EVENT SHALL THE AUTHORS~~
	~~OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM~~, ~~DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR~~
	~~OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE~~.~~</ref>~~
	~~The presentation can also be found in~~ the ~~uvvm_util folder.~~

	== Introduction ==		== Introduction ==
			UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for making very structured VHDL-based testbenches, examples and simulations scripts from the [https://github.com/UVVM/UVVM UVVM on github].
	~~Bitvis~~ UVVM ~~VVC Framework~~ is a ~~complete framework~~ for making VHDL testbenches ~~for~~
	~~verification of FPGA and ASIC desing. You can download the complete code-base~~, examples and simulations scripts from the [https://github.com/UVVM/~~UVVM_All Bitvis~~ github].

	=== What's in the folders? ===		=== What's in the folders? ===
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	==Simulation==		==Simulation==
	We now have the skeleton of the testbench, which we will develop further. But now, let's see if everything works. ~~Bitvis have created~~ simulation scripts for the IRQC example that compiles everything we need, from the source files of the VHDL design, to the testbench (if you called the file irqc_tb.vhd and placed it in the tb-folder) and the SBI BFM and the UVVM library. Open up QuestaSim/ModelSim.		We now have the skeleton of the testbench, which we will develop further. But now, let's see if everything works. UVVM includes simulation scripts for the IRQC example that compiles everything we need, from the source files of the VHDL design, to the testbench (if you called the file irqc_tb.vhd and placed it in the tb-folder) and the SBI BFM and the UVVM library. Open up QuestaSim/ModelSim.
	Change directory to the script folder (where you have copied the UVVM files), for example in phys321/bitviswiki.....:		Change directory to the script folder (where you have copied the UVVM files), for example in phys321/bitviswiki.....:
	<pre>		<pre>
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	</pre>		</pre>

	All this enables us to handle transactions at a high level. See ~~Bitvis~~ documentation for how to write your own BFM and what it should include(sanity checks, etc).		All this enables us to handle transactions at a high level. See UVVM documentation for how to write your own BFM and what it should include(sanity checks, etc).

	[[File:bfm.png\|550px]]		[[File:bfm.png\|550px]]

Nfyku: /* Simulation */

2024-02-13T12:14:01Z

Simulation

← Older revision		Revision as of 12:14, 13 February 2024
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	==Simulation==		==Simulation==
	We now have the skeleton of the testbench, which we will develop further. But now, let's see if everything works. Bitvis have created simulation scripts for the IRQC example that compiles everything we need, from the source files of the VHDL design, to the testbench (if you called the file irqc_tb.vhd and placed it in the tb-folder) and the SBI BFM and the UVVM library. Open up QuestaSim/ModelSim.		We now have the skeleton of the testbench, which we will develop further. But now, let's see if everything works. Bitvis have created simulation scripts for the IRQC example that compiles everything we need, from the source files of the VHDL design, to the testbench (if you called the file irqc_tb.vhd and placed it in the tb-folder) and the SBI BFM and the UVVM library. Open up QuestaSim/ModelSim.
	Change directory to the script folder:		Change directory to the script folder (where you have copied the UVVM files), for example in phys321/bitviswiki.....:
	<pre>		<pre>
	cd ~/phys321/bitviswiki/bitvis_irqc/script		cd ~/phys321/bitviswiki/bitvis_irqc/script

Kaf003: Added some text recommending not including an overload

2021-03-09T15:48:21Z

Added some text recommending not including an overload

← Older revision		Revision as of 15:48, 9 March 2021
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	end;		end;
	</pre>		</pre>

			This exact function is already overloaded in the UVVM packages, so including this in our testbench would produce compilation errors. So, let's not include it, but view it as an example of how it's done.

	Let's say that it is probable that we'll want to change the number of interrupt sources that the controller can handle. We will then want to able to easily change vectors to the appropriate size. One way is to declare procedures that can trim and fit vectors. This way we can simply change a constant to change the number of sources.		Let's say that it is probable that we'll want to change the number of interrupt sources that the controller can handle. We will then want to able to easily change vectors to the appropriate size. One way is to declare procedures that can trim and fit vectors. This way we can simply change a constant to change the number of sources.

Kaf003: Included the need to set sbi_if.ready signal high to avoid failure.

2021-03-09T15:42:32Z

Included the need to set sbi_if.ready signal high to avoid failure.

← Older revision		Revision as of 15:42, 9 March 2021
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	clk, sbi_if, C_SCOPE);		clk, sbi_if, C_SCOPE);
	end;		end;
			</pre>

			We also need to set the sbi_if.ready signal high for this to work:
			<pre>
			clock_generator(clk, clock_ena, C_CLK_PERIOD, "IRQC TB clock");

			-- Insert this here by the clock generator
			sbi_if.ready <= '1'; -- always ready in the same clock cycle.
	</pre>		</pre>

Kaf003: Changed position of alert_level to where it should be

2021-03-09T15:04:22Z

Changed position of alert_level to where it should be

← Older revision		Revision as of 15:04, 9 March 2021
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	constant addr_value : in unsigned;		constant addr_value : in unsigned;
	constant data_exp : in std_logic_vector;		constant data_exp : in std_logic_vector;
	~~constant alert_level : in t_alert_level := error;~~
	constant msg : in string;		constant msg : in string;
	signal clk : in std_logic;		signal clk : in std_logic;
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	signal ready : in std_logic;		signal ready : in std_logic;
	signal rdata : in std_logic_vector;		signal rdata : in std_logic_vector;
			constant alert_level : in t_alert_level := error;
	constant scope : in string := C_SCOPE;		constant scope : in string := C_SCOPE;
	constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;		constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
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	constant msg : in string) is		constant msg : in string) is
	begin		begin
	sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp~~, alert_level~~, msg,		sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,
	clk, sbi_if, C_SCOPE);		clk, sbi_if, alert_level, C_SCOPE);
	end;		end;
	</pre>		</pre>

Kaf003: Reverted edits by Kaf003 (talk) to last revision by Put009

2021-03-09T15:03:02Z

Reverted edits by Kaf003 (talk) to last revision by Put009

← Older revision		Revision as of 15:03, 9 March 2021
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	constant addr_value : in unsigned;		constant addr_value : in unsigned;
	constant data_exp : in std_logic_vector;		constant data_exp : in std_logic_vector;
			constant alert_level : in t_alert_level := error;
	constant msg : in string;		constant msg : in string;
	signal clk : in std_logic;		signal clk : in std_logic;
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	signal ready : in std_logic;		signal ready : in std_logic;
	signal rdata : in std_logic_vector;		signal rdata : in std_logic_vector;
	~~constant alert_level : in t_alert_level := error;~~
	constant scope : in string := C_SCOPE;		constant scope : in string := C_SCOPE;
	constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;		constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
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	constant msg : in string) is		constant msg : in string) is
	begin		begin
	sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,		sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, alert_level, msg,
	clk, sbi_if~~, alert_level~~, C_SCOPE);		clk, sbi_if, C_SCOPE);
	end;		end;
	</pre>		</pre>

Kaf003 at 15:02, 9 March 2021

2021-03-09T15:02:52Z

← Older revision		Revision as of 15:02, 9 March 2021
Line 421:		Line 421:
	constant addr_value : in unsigned;		constant addr_value : in unsigned;
	constant data_exp : in std_logic_vector;		constant data_exp : in std_logic_vector;
	~~constant alert_level : in t_alert_level := error;~~
	constant msg : in string;		constant msg : in string;
	signal clk : in std_logic;		signal clk : in std_logic;
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	signal ready : in std_logic;		signal ready : in std_logic;
	signal rdata : in std_logic_vector;		signal rdata : in std_logic_vector;
			constant alert_level : in t_alert_level := error;
	constant scope : in string := C_SCOPE;		constant scope : in string := C_SCOPE;
	constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;		constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
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	constant msg : in string) is		constant msg : in string) is
	begin		begin
	sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp~~, alert_level~~, msg,		sbi_check(to_unsigned(addr_value, sbi_if.addr'length), data_exp, msg,
	clk, sbi_if, C_SCOPE);		clk, sbi_if, alert_level, C_SCOPE);
	end;		end;
	</pre>		</pre>

Put009: Corrected write and read signal names in set_inputs_passive and fixed dead link

2018-03-08T13:18:14Z

Corrected write and read signal names in set_inputs_passive and fixed dead link

← Older revision		Revision as of 13:18, 8 March 2018
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	OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR		OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</ref>		OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.</ref>
			The presentation can also be found in the uvvm_util folder.

	== Introduction ==		== Introduction ==

	Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for		Bitvis UVVM VVC Framework is a complete framework for making VHDL testbenches for
	verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the [~~http~~://~~bitvis~~.no/~~products/uvvm-vvc-framework~~/ Bitvis ~~web page~~].		verification of FPGA and ASIC desing. You can download the complete code-base, examples and simulations scripts from the [https://github.com/UVVM/UVVM_All Bitvis github].

	=== What's in the folders? ===		=== What's in the folders? ===
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	sbi_if.cs <= '0';		sbi_if.cs <= '0';
	sbi_if.addr <= (others => '0');		sbi_if.addr <= (others => '0');
	sbi_if.wr <= '0';		sbi_if.wena <= '0';
	sbi_if.rd <= '0';		sbi_if.rena <= '0';
	sbi_if.wdata <= (others => '0');		sbi_if.wdata <= (others => '0');
	irq_source <= (others => '0');		irq_source <= (others => '0');

Fli091: Added Category:Mikroelektronikk to this page so its listed

2017-09-15T12:16:22Z

Added Category:Mikroelektronikk to this page so its listed

← Older revision		Revision as of 12:16, 15 September 2017
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	== UVVM LICENCE AGREEMENT ==		== UVVM LICENCE AGREEMENT ==
	{{reflist}}		{{reflist}}

			[[Category:Mikroelektronikk]]