BGO-firmware-structure - Revision history

Ako054: /* Memory bus interface (mb_if) */

2010-10-13T14:46:20Z

Memory bus interface (mb_if)

@@ Line 43: / Line 43: @@
 ====Memory bus interface (mb_if)====
-including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.
+see [[#Memory_bus_interface_.28mb_if.29_3|mb_if ]] in Temperature Monitor
 ====mov_avrg and mov_avrg8====

2010-10-13T14:45:57Z

memory bus interface (mb_if)

← Older revision		Revision as of 14:45, 13 October 2010
Line 147:		Line 147:
	===swing buffer===		===swing buffer===
	===bin module address arbiter===		===bin module address arbiter===
	===~~memory~~ bus interface (mb_if)===		===Memory bus interface (mb_if)===
	see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in ~~BGO channel~~		see [[#Memory_bus_interface_.28mb_if.29_3\|mb_if ]] in Temperature Monitor

	==DPU interface (dpu_if)==		==DPU interface (dpu_if)==

2010-10-13T14:44:42Z

memory bus interface

← Older revision		Revision as of 14:44, 13 October 2010
Line 207:		Line 207:
	* asim_common_lib		* asim_common_lib

	===~~memory~~ bus interface===		===Memory bus interface (mb_if)===
	for communication with user interface.		for communication with user interface.
	including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.		including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

2010-10-13T14:44:18Z

memory bus interface

← Older revision		Revision as of 14:44, 13 October 2010
Line 220:		Line 220:
	* memdat_out (to address decoder, incl. answer)		* memdat_out (to address decoder, incl. answer)
	* control registers cr[0-3] (to logig module, incl. command)		* control registers cr[0-3] (to logig module, incl. command)


	general:		general:
	* asim_common_lib		* asim_common_lib
	* by yngve 2008		* by yngve 2008

2010-10-13T14:44:05Z

memory bus interface

@@ Line 209: / Line 209: @@
 ===memory bus interface===
 for communication with user interface.
 * asim_common_lib
-* 2008 by yngve (auto)
+* by yngve 2008

2010-10-13T14:42:48Z

memory bus interface (mb_if)

← Older revision		Revision as of 14:42, 13 October 2010
Line 148:		Line 148:
	===bin module address arbiter===		===bin module address arbiter===
	===memory bus interface (mb_if)===		===memory bus interface (mb_if)===
	see mb_if		see [[#Memory_bus_interface_.28mb_if.29\|mb_if ]] in BGO channel

	==DPU interface (dpu_if)==		==DPU interface (dpu_if)==

2010-10-13T14:39:31Z

memory bus interface

2010-10-13T14:37:52Z

mb_if

← Older revision		Revision as of 14:37, 13 October 2010
Line 42:		Line 42:
	</pre>		</pre>

	====mb_if====		====Memory bus interface (mb_if)====
	~~Memory bus interface.~~		including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.
	including a control register and a fsm. basically a translator.

	translating memory data into commands for active module and delivers status reports.


	'''input:'''		'''input:'''

2010-10-13T14:37:05Z

mb_if

← Older revision		Revision as of 14:37, 13 October 2010
Line 45:		Line 45:
	Memory bus interface.		Memory bus interface.
	including a control register and a fsm. basically a translator.		including a control register and a fsm. basically a translator.

	translating memory data into commands for active module and delivers status reports.		translating memory data into commands for active module and delivers status reports.

2010-10-13T14:33:43Z

mb_if

@@ Line 44: / Line 44: @@
 ====mb_if====
 Memory bus interface.
 * asim_common_lib
 * by yngve 2008