ift - User contributions [en]

User:Yag005

2019-03-02T16:52:10Z

Yag005: Updated information and added link to thesis

yag005 is the username for Mats F. Heigre.
Mats was part of the microelectronics group in the period August 2016 until he delivered his master thesis and thus finishing his degree in October 2018.
His master thesis, Design of an Embedded Readout System for the ALOFT Gamma-Ray Detector Instrument, can be found at BORA under the following link: [http://bora.uib.no/handle/1956/18671 http://bora.uib.no/handle/1956/18671]

Contact email: yag005@student.uib.no

Running FreeRTOS on Xilinx Zybo

2018-01-09T13:58:17Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
Tutorial heavily based on:
#REDIRECT [[http://rishifranklin.blogspot.no/2015/04/freertos-on-xilinx-zynq-zybo-single-core.html]]
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
platform.c 
platform.h 
platform_config.h
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder to contain "*(.freertos_vectors)":
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px|center]]

= Write the application =
Go back into Xilinx SDK and refresh(F5). All the added files should now be visible in the project explorer.

Open main.c, and comment out the call to ''vParTestInitialise()'' from the ''prvSetupHardware'' function as it is not related to the Zybo board.
Also comment out all the included headerfiles under "Standard Demo Include: 
[[File:remove_include_demo_libs.png|400px|center]] 

Also set ''#define mainSELECTED_APPLICATION 0'' instead of 1. It should be located around line 141.
Add ''#define AXI_LED_BASE 0x43c30000'' somewhere in the top of the code, but not within any functions, for example right after all the #includes.

Time to write the actual code. Add the following as a function before main:
[[File:AXILedBlink_code.png|400px|center]] 
 
The last thing we need to do code vise, is to call the function we just created in the main function:
[[File:main_code.png|400px|center]] 
 
Save, then goto ''Project --> Build All''.

Time to test the software! Bring up your favorite Xilinx Zybo SoC board, and ensure that jumper 5 (JP5) is configured for booting via JTAG. Connect the board to the computer, and power it up. Then in Xilinx SDK, goto ''Xilinx --> Program FPGA''. If successful, goto ''Run --> Run as --> 1 Launch on Hardware (System Debugger)''. The 4 LEDs on the board should now light up and blink.

End of tutorial!

Running concurrent application projects in Xilinx SDK

2018-01-04T15:19:45Z

Yag005:

Tested on Xilinx SDK 2017.4, with Xilinx Digilent Zybo SoC.

= Running concurrent application projects in Xilinx SDK =
This tutorial gives a brief introduction to running concurrent application projects in Xilinx SDK on a micro processor. This is done by assigning each of the Application Projects a specific processor core to run on.

= Requirements =

This tutorial requires a multi-core micro processor system that can be programmed by Xilinx SDK. It also assumes that the user has two working independent Project applications with respective Board Support Packages (BSP's) generated by the "File --> New --> Project Application" menu.

= Assigning application project to specific processor core =
Click once on one of the Application projects in the Project Explorer Tree.

Goto: "Run --> Run Configurations". Then click on "System Debugger using Debug_standalone_bsp_0_NAMEOFYOURPROJECT.elf on Local" under "Xilinx C/C++ application (SystemDebugger).
Then open the Application tab. You should now see that your application is configured in the Summary window to run on core 0 on whatever processor you're using. [[File:running_concurrent_xilinx_sdk_not_added.png|400px|thumbnail|center]]

The next step is to take use of the other processor core, by assigning it the other application project you want to run. Click on the line with the processor core you want to use (ps7_cortexa9_1 for this tutorial), mark "Download", and click on Browse in the Application bar. Find the nameofproject.elf file for the application project, usually found under /NameOfVivadoProject.sdk/NameOfProject/Debug/NameOfProject.elf. For this tutorial we added the FreeRTOS.elf created in the [[Running FreeRTOS on Xilinx Zybo]]-tutorial.
It should now look like this:
[[File:running_concurrent_xilinx_sdk_added.png|400px|thumbnail|center]]

Click Apply, and run. This should program the processor over JTAG, and both applications should be up and running.

Running concurrent application projects in Xilinx SDK

2018-01-04T15:19:13Z

Yag005: Created page with "Tested on Xilinx SDK 2017.4, with Xilinx Digilent Zybo SoC. = Running concurrent application projects in Xilinx SDK = This tutorial gives a brief introduction to running conc..."

Tested on Xilinx SDK 2017.4, with Xilinx Digilent Zybo SoC.

= Running concurrent application projects in Xilinx SDK =
This tutorial gives a brief introduction to running concurrent application projects in Xilinx SDK on a micro processor. This is done by assigning each of the Application Projects a specific processor core to run on.

= Requirements =

This tutorial requires a multi-core micro processor system that can be programmed by Xilinx SDK. It also assumes that the user has two working independent Project applications with respective Board Support Packages (BSP's) generated by the "File --> New --> Project Application" menu.

= Assigning application project to specific processor core =
Click once on one of the Application projects in the Project Explorer Tree.

Goto: "Run --> Run Configurations". Then click on "System Debugger using Debug_standalone_bsp_0_NAMEOFYOURPROJECT.elf on Local" under "Xilinx C/C++ application (SystemDebugger).
Then open the Application tab. You should now see that your application is configured in the Summary window to run on core 0 on whatever processor you're using. [[File:running_concurrent_xilinx_sdk_not_added.png|400px|thumbnail]]

The next step is to take use of the other processor core, by assigning it the other application project you want to run. Click on the line with the processor core you want to use (ps7_cortexa9_1 for this tutorial), mark "Download", and click on Browse in the Application bar. Find the nameofproject.elf file for the application project, usually found under /NameOfVivadoProject.sdk/NameOfProject/Debug/NameOfProject.elf. For this tutorial we added the FreeRTOS.elf created in the [[Running FreeRTOS on Xilinx Zybo]]-tutorial.
It should now look like this:
[[File:running_concurrent_xilinx_sdk_added.png|400px|thumbnail]]

Click Apply, and run. This should program the processor over JTAG, and both applications should be up and running.

File:Running concurrent xilinx sdk added.png

2018-01-04T15:17:11Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

File:Running concurrent xilinx sdk not added.png

2018-01-04T15:08:06Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

Xilinx SDK

2018-01-04T14:32:00Z

Yag005: Created page with "Running concurrent application projects in Xilinx SDK"

[[Running concurrent application projects in Xilinx SDK]]

Xilinx Vivado

2018-01-04T14:31:21Z

Yag005: Created page with "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"

[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]

Microelectronics group

2018-01-04T14:30:22Z

Yag005:

== Øvinger og guider ==
=== Mentor Graphics ===

* [[Expedition PCB]] Komme i gang med kretskortutlegg ved hjelp av Expedition PCB

* [[Modelsim/Questa]] Skrive og simulere VHDL-kode med Mentor Graphics ModelSim

=== Cadence ===

* [[Cadence Virtuoso]]

=== Microsemi ===

* [[SmartFusion2- AMBA APB, Custom Peripheral]] Making a custom peripheral for the AMBA APB bus

=== Xilinx ===

* [[Xilinx Vivado]] Tutorials for Xilinx Vivado

* [[Xilinx SDK]] Tutorials for Xilinx Software Development Kit

=== Annet ===
* [[Bitvis UVVM VHDL Verification Component Framework]]

* [[Tutorials]] Tutorials from the web

* [[XJTAG]] Boundary Scan with XJTAG

* [[XJDeveloper]] Innføring i XJDeveloper

* [[FreeRTOS]] Free Real Time Operating System

== Andre fagressurser og laboratorieveiledninger==

* [[PHYS222]] Fagressurser for PHYS222 og PHYS223

* [[PHYS321]] Fagressurser for PHYS321

* [[Teknisk hjelp]] Teknisk hjelp for bruk av DAK-programvare

* [[BGA lodding]] bruk av Martin 09.6 XL BGA lodding maskin (intern)

* [[Reflow Soldering]] Use of Technoprint HA-02 reflow oven

== Eldre øvinger og guider ==
=== Mentor Graphics ===
* [[IC studio]] Veiledning til IC-design ved hjelp av IC studio

* [[IC studio - SPICE/Symbol Tutorial]] Relate a SPICE file to a Symbol

* [[IC Station]] Tegne utlegg for integrerte kretser

=== Annet ===
* [[PCI-eksperiment]] Øving med HLT-RORC-prototypekort

* [[Xilinx]] Øving i bruk av Xilinx Project Studio

* [[SmartFusion2]] Oppsett og design med SF2

* [[FLTK GUI]] Graphical User Interface using FLTK

[[Category:Mikroelektronikk]]

Microelectronics group

2018-01-04T14:27:58Z

Yag005: Added Xilinx to comply with readability criteria.

== Øvinger og guider ==
=== Mentor Graphics ===

* [[Expedition PCB]] Komme i gang med kretskortutlegg ved hjelp av Expedition PCB

* [[Modelsim/Questa]] Skrive og simulere VHDL-kode med Mentor Graphics ModelSim

=== Cadence ===

* [[Cadence Virtuoso]]

=== Microsemi ===

* [[SmartFusion2- AMBA APB, Custom Peripheral]] Making a custom peripheral for the AMBA APB bus

=== Xilinx ===

* [[Vivado]] Xilinx Vivado

* [[SDK]] Xilinx Software Development Kit

=== Annet ===
* [[Bitvis UVVM VHDL Verification Component Framework]]

* [[Tutorials]] Tutorials from the web

* [[XJTAG]] Boundary Scan with XJTAG

* [[XJDeveloper]] Innføring i XJDeveloper

* [[FreeRTOS]] Free Real Time Operating System

== Andre fagressurser og laboratorieveiledninger==

* [[PHYS222]] Fagressurser for PHYS222 og PHYS223

* [[PHYS321]] Fagressurser for PHYS321

* [[Teknisk hjelp]] Teknisk hjelp for bruk av DAK-programvare

* [[BGA lodding]] bruk av Martin 09.6 XL BGA lodding maskin (intern)

* [[Reflow Soldering]] Use of Technoprint HA-02 reflow oven

== Eldre øvinger og guider ==
=== Mentor Graphics ===
* [[IC studio]] Veiledning til IC-design ved hjelp av IC studio

* [[IC studio - SPICE/Symbol Tutorial]] Relate a SPICE file to a Symbol

* [[IC Station]] Tegne utlegg for integrerte kretser

=== Annet ===
* [[PCI-eksperiment]] Øving med HLT-RORC-prototypekort

* [[Xilinx]] Øving i bruk av Xilinx Project Studio

* [[SmartFusion2]] Oppsett og design med SF2

* [[FLTK GUI]] Graphical User Interface using FLTK

[[Category:Mikroelektronikk]]

FreeRTOS FSBL

2017-12-06T18:23:32Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.

This tutorial assumes you have completed the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

===== Creating FSBL =====

The result from the previous tutorial linked at the top of this tutorial, should be a Project Explorer looking like this:
[[File:project_explorer_start.png|400px|center]] 

Goto ''File --> New --> Application Project''. Name the new project "FSBL" and let OS platform be "standalone". On the next page, choose the "Zynq FSBL"-template. Finish.
The Project Explorer should now contain the following:
[[File:fsbl_created.png|400px|center]] 

Goto ''Xilinx --> Create Boot Image''. Choose the Zynq architecture and click to browse for a Output BIF file path. Name the file "output.bif" and create a folder called "output" within the axi4_lite_tutorial_project.sdk directory. Click OK.
Check that the output format is "BIN". Now click add in the Boot Image Partitions section:

Choose "Bootloader" as partition type, and navigate to the file "FSBL.elf" under \axi4_lite_tutorial_project.sdk\FSBL\Debug\ in the file path. 
Now add a new partition, this time as type "datafile". The file that should be added to file path is "design_1_wrapper.bit" under \axi4_lite_tutorial_project.runs\impl_1\ 
The third and final partition is of type "datafile", has the name "FreeRTOS_example_project.elf", and is found at \axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\Debug\ 
 
When all partitions have been added, click "Create Image". Navigate to the directory you specified for output, in our case \axi4_lite_tutorial_project.sdk\output.
It should now contain two files: BOOT.bin, and output.bif. Copy the BOOT.bin file onto an SD-card formatted as FAT.

Bring up your favorite Xilinx Zybo SoC board, and configure jumper 5 (JP5) for SD boot configuration. Insert the SD card, and connect a power source (wall or USB). Then power up the board. After a couple of seconds, it should behave just as it did when booting from JTAG in the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

FreeRTOS FSBL

2017-12-06T18:22:13Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.

This tutorial assumes you have completed the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

===== Creating FSBL =====

The result from the previous tutorial linked at the top of this tutorial, should be a Project Explorer looking like this:
[[File:project_explorer_start.png|400px|center]] 

Goto ''File --> New --> Application Project''. Name the new project "FSBL" and let OS platform be "standalone". On the next page, choose the "Zynq FSBL"-template. Finish.
The Project Explorer should now contain the following:
[[File:fsbl_created.png|400px|center]] 

Goto ''Xilinx --> Create Boot Image''. Choose the Zynq architecture and click to browse for a Output BIF file path. Name the file "output.bif" and create a folder called "output" within the axi4_lite_tutorial_project.sdk directory. Click OK.
Check that the output format is "BIN". Now click add in the Boot Image Partitions section:

Choose "Bootloader" as partition type, and navigate to the file "FSBL.elf" under \axi4_lite_tutorial_project.sdk\FSBL\Debug\ in the file path. 
Now add a new partition, this time as type "datafile". The file that should be added to file path is "design_1_wrapper.bit" under \axi4_lite_tutorial_project.runs\impl_1\ 
The third and final partition: Partition type "datafile", name: FreeRTOS_example_project.elf File path: \axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\Debug\ 
 
When all partitions have been added, click "Create Image". Navigate to the directory you specified for output, in our case \axi4_lite_tutorial_project.sdk\output.
It should now contain two files: BOOT.bin, and output.bif. Copy the BOOT.bin file onto an SD-card formatted as FAT.

Bring up your favorite Xilinx Zybo SoC board, and configure jumper 5 (JP5) for SD boot configuration. Insert the SD card, and connect a power source (wall or USB). Then power up the board. After a couple of seconds, it should behave just as it did when booting from JTAG in the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

FreeRTOS FSBL

2017-12-06T17:53:43Z

Yag005:

File:Fsbl created.png

2017-12-06T17:53:30Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

File:Project explorer start.png

2017-12-06T17:49:01Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

Running FreeRTOS on Xilinx Zybo

2017-12-06T17:44:53Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
Tutorial heavily based on:
#REDIRECT [[http://rishifranklin.blogspot.no/2015/04/freertos-on-xilinx-zynq-zybo-single-core.html]]
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
platform.c 
platform.h 
platform_config.h
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px|center]]

= Write the application =
Go back into Xilinx SDK and refresh(F5). All the added files should now be visible in the project explorer.

Open main.c, and comment out the call to ''vParTestInitialise()'' from the ''prvSetupHardware'' function as it is not related to the Zybo board.
Also comment out all the included headerfiles under "Standard Demo Include: 
[[File:remove_include_demo_libs.png|400px|center]] 

Also set ''#define mainSELECTED_APPLICATION 0'' instead of 1. It should be located around line 141.
Add ''#define AXI_LED_BASE 0x43c30000'' somewhere in the top of the code, but not within any functions, for example right after all the #includes.

Time to write the actual code. Add the following as a function before main:
[[File:AXILedBlink_code.png|400px|center]] 
 
The last thing we need to do code vise, is to call the function we just created in the main function:
[[File:main_code.png|400px|center]] 
 
Save, then goto ''Project --> Build All''.

Time to test the software! Bring up your favorite Xilinx Zybo SoC board, and ensure that jumper 5 (JP5) is configured for booting via JTAG. Connect the board to the computer, and power it up. Then in Xilinx SDK, goto ''Xilinx --> Program FPGA''. If successful, goto ''Run --> Run as --> 1 Launch on Hardware (System Debugger)''. The 4 LEDs on the board should now light up and blink.

End of tutorial!

File:Main code.png

2017-12-06T17:35:42Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

File:AXILedBlink code.png

2017-12-06T17:32:58Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

Running FreeRTOS on Xilinx Zybo

2017-12-06T17:26:22Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
platform.c 
platform.h 
platform_config.h
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px|center]]

= Write the application =
Go back into Xilinx SDK and refresh(F5). All the added files should now be visible in the project explorer.

Open main.c, and comment out the call to ''vParTestInitialise()'' from the ''prvSetupHardware'' function as it is not related to the Zybo board.
Also comment out all the included headerfiles under "Standard Demo Include: 
[[File:remove_include_demo_libs.png|400px|center]] 

Also set ''#define mainSELECTED_APPLICATION 0'' instead of 1. It should be located around line 141.

File:Remove include demo libs.png

2017-12-06T17:24:00Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

File:Source folder.png

2017-12-06T17:05:49Z

Yag005: Yag005 uploaded a new version of File:Source folder.png

File uploaded with MsUpload

Running FreeRTOS on Xilinx Zybo

2017-12-06T17:01:26Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
platform.c 
platform.h 
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px|center]]

= Write the application =
Go back into Xilinx SDK and refresh(F5). All the added files should now be visible in the project explorer.

File:Source folder.png

2017-12-06T16:04:11Z

Yag005: Yag005 uploaded a new version of File:Source folder.png

File uploaded with MsUpload

Running FreeRTOS on Xilinx Zybo

2017-12-06T16:00:46Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px|center]]

= Write the application =
Go back into Xilinx SDK and refresh(F5). All the added files should now be visible in the project explorer.

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:53:45Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px|center]]

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:52:54Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

= Setting CPU frequency =

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px]|center]

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:51:50Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.
This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

= Running FreeRTOS on Xilinx Zybo =

This tutorial will help in setting up Xilinx Zybo SoC-board to run FreeRTOS with an example project that toggles the LEDs on the board.
It assumes that the user has successfully exported the hardware bitstream from the Xilinx Vivado project created in the previous tutorial linked at the top.

= Setup SDK =
Launch Xilinx SDK from the project in Xilinx Vivado: ''File --> Launch SDK''.

Create a new application project with ''File --> New --> Application Project'' and name it "FreeRTOS_example_project". Use C as language, standalone as OS. Click next, select "Empty Application", and finish.

= Acquire FreeRTOS =
Download and extract FreeRTOS available at the FreeRTOS homepage:
#Homepage [[https://www.freertos.org/a00104.html]] 

= Add FreeRTOS to the project =
Open the extracted folder, and copy the following files into the SDK project source folder located at: \axi3_lite_tutorial_project\axi4_lite_tutorial_project.sdk\FreeRTOS_example_project\src\

\FreeRTOSV8.2.1\FreeRTOS\Demo\CORTEX_A9_Zynq_ZC702\RTOSDemo\src\ 
FreeRTOS_asm_vectors.S 
FreeRTOSConfig.h 
FreeRTOS_tick_config.c 
main.c 
printf-stdarg.c 
 

\FreeRTOSV8.2.1\FreeRTOS\Source\ 
croutine.c 
event_groups.c 
list.c 
queue.c 
tasks.c 
timers.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\include\ 
croutine.h 
deprecated_definitions.h 
event_groups.h 
FreeRTOS.h 
list.h 
mpu_prototypes.h 
mpu_wrappers.h 
portable.h 
projdefs.h 
queue.h 
semphr.h 
StackMacros.h 
task.h 
timers.h 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\MemMang\ 
heap_4.c 

\FreeRTOSV8.2.1\FreeRTOS\Source\portable\GCC\ARM_CA9\ 
port.c 
portASM.S 
portmacro.h 
 

Your SDK project source folder should now look like this:
[[File:source_folder.png|thumbnail|center]] 

Edit the highlighted line to the lscript.id file located in the SDK project source folder:
[[File:lscript_id_edit.png|400px|center]] 

Comment out "*pxTopOfStack |= portTHUMB_MODE_BIT;" on line 280 in port.c to avoid FreeRTOS to run in thumb-mode:
[[File:port_c_edit.png|400px|center]] 
 

Next we should configure the CPU to run at 50MHz in the FreeRTOSConfig.h file by editing the configCPU_CLOCK_HZ parameter:
[[File:FreeRTOSConfig_cpu_freq_edit.png|400px]|center]

File:FreeRTOSConfig cpu freq edit.png

2017-12-06T15:51:30Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

File:Port c edit.png

2017-12-06T15:46:43Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

File:Lscript id edit.png

2017-12-06T15:39:41Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:23:53Z

Yag005:

File:Source folder.png

2017-12-06T15:23:38Z

Yag005: File uploaded with MsUpload

File uploaded with MsUpload

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:19:48Z

Yag005:

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:16:55Z

Yag005:

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:11:10Z

Yag005:

Running FreeRTOS on Xilinx Zybo

2017-12-06T15:03:51Z

Yag005:

Running FreeRTOS on Xilinx Zybo

2017-12-06T14:58:50Z

Yag005:

Microelectronics group

2017-12-06T13:29:31Z

Yag005:

== Øvinger og guider ==
=== Mentor Graphics ===

* [[Expedition PCB]] Komme i gang med kretskortutlegg ved hjelp av Expedition PCB

* [[Modelsim/Questa]] Skrive og simulere VHDL-kode med Mentor Graphics ModelSim

=== Cadence ===

* [[Cadence Virtuoso]]

=== Microsemi ===

* [[SmartFusion2- AMBA APB, Custom Peripheral]] Making a custom peripheral for the AMBA APB bus

=== Annet ===
* [[Bitvis UVVM VHDL Verification Component Framework]]

* [[Tutorials]] Tutorials from the web

* [[XJTAG]] Boundary Scan with XJTAG

* [[XJDeveloper]] Innføring i XJDeveloper

* [[FreeRTOS]] Free Real Time Operating System

* [[Vivado]] Xilinx Vivado

== Andre fagressurser og laboratorieveiledninger==

* [[PHYS222]] Fagressurser for PHYS222 og PHYS223

* [[PHYS321]] Fagressurser for PHYS321

* [[Teknisk hjelp]] Teknisk hjelp for bruk av DAK-programvare

* [[BGA lodding]] bruk av Martin 09.6 XL BGA lodding maskin (intern)

* [[Reflow Soldering]] Use of Technoprint HA-02 reflow oven

== Eldre øvinger og guider ==
=== Mentor Graphics ===
* [[IC studio]] Veiledning til IC-design ved hjelp av IC studio

* [[IC studio - SPICE/Symbol Tutorial]] Relate a SPICE file to a Symbol

* [[IC Station]] Tegne utlegg for integrerte kretser

=== Annet ===
* [[PCI-eksperiment]] Øving med HLT-RORC-prototypekort

* [[Xilinx]] Øving i bruk av Xilinx Project Studio

* [[SmartFusion2]] Oppsett og design med SF2

* [[FLTK GUI]] Graphical User Interface using FLTK

[[Category:Mikroelektronikk]]

Running FreeRTOS on Xilinx Zybo

2017-12-06T13:26:34Z

Yag005:

Creating example project with AXI4 Lite peripheral in Xilinx Vivado

2017-12-06T13:25:42Z

Yag005:

Tested on Xilinx Vivado 2017.3, using the Xilinx Digilent Zybo SoC.

= Create a Project =

Start ./vivado from installed directory.
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]

Do not add any sources, but make sure that both target and simulator language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.
Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub]. Make sure that the option to copy the constraints file(s) into the project is marked.

For the next step, the board files for the board we're using must have been installed. If this is not the case, follow [https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 this tutorial] to do so. [[File:new_project_default_part.png|thumbnail|center]]
Choose the Zybo board, click next, and finish.

= Creating a block desgin =

The project has now been created and ready for IP-block integration.
Click on "Create Block Design" in the left of the window. Give the design a name, for instance design_1, and click "OK".[[File:create_block_design.png|thumbnail|center]]

Now press the "+" button in the diagram window, and search for "ZYNQ7 Processing System". Double click to add. In the top of the window an option to "Run Block Automation" appears.. Click this, and complete with default settings. The window should now look like this: [[File:first_block.png|thumbnail|center]]

= Create a Custom AXI4-lite IP block =
Goto: ''Tools -> Create and Package New IP''. Choose "Create a New AXI4 peripheral", and click next.
Name the IP "axi4_lite_led_IP" or any other suiting name. You can leave all other parameters default.
In the next window, ensure the IP contains one slave interface named S00_AXI of type "Lite". Click next, and choose "Add IP to the repository". Finish.[[File:add_interfaces_axi4lite.png|thumbnail|center]]

In the diagram window it's now possible to add the IP we just created, using the "+" button. Search for "axi4_lite_led_IP_v1.0" and add it. Run connection/block automation with default parameters.

[[File:diagram_axi4lite_periph_added.png|center]] 

Right click on "design_1" under "Block Designs" in the Sources design tree. Click "Create HDL Wrapper", and let Vivado manage wrapper and auto-update.

''Right click axi4_lite_led_IP_0 block --> Edit in IP Packager''. Then do the following edits to axi4_lite_led_IP_v1_0_S00_AXI.vhd and axi4_lite_led_IP_v1_0.vhd 
 

[[File:led_ip_1.png|400px]]
[[File:led_ip_2.png|400px]]
[[File:led_ip_3.png|400px]]
[[File:S00_1.png|400px]]
[[File:S00_2.png|400px]]

Save both files, and go into the "Ports and interfaces" tab. Click "Merge changes from Ports and Interfaces Wizard". A new port should now be listed named "led_port". Click on "Review and Package", and click Re-Package IP. Click yes on prompt to close project.

Click on "IP Status" tab, and choose "Upgrade Selected" if you are not automatically prompted. Go back to the Block design diagram, and right-click on the newly created port named "led_port[3:0]" on our custom IP and choose "make external". Save.

= Editing the Constraints file =

Open the constraints file ZYBO_Master.xdc located under Constraints in the sources tab design tree.
To avoid tons of warnings, comment out everything except from the 4 lines under "##LEDs" since we're only using them for this project.
Rewrite them to the following: 

set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led_port[3] }]; 
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led_port[2] }]; 
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led_port[1] }]; 
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led_port[0] }]; 

Save the file, and click "Generate Bitstream". Accept the launch of synthesis and implementation.
When complete, you can choose to open the implemented design and have a look at it, or specify timing restraints.

= Exporting Bitstream =

Goto: ''File --> Export --> Export Hardware'', and choose to include bitstream.

You are now done with this tutorial.

Creating example project with AXI4 Lite peripheral in Xilinx Vivado

2017-12-06T13:23:12Z

Yag005:

Tested on Xilinx Vivado 2017.3, using the Xilinx Digilent Zybo SoC.

Start ./vivado from installed directory.
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]

Do not add any sources, but make sure that both target and simulator language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.
Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub]. Make sure that the option to copy the constraints file(s) into the project is marked.

For the next step, the board files for the board we're using must have been installed. If this is not the case, follow [https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 this tutorial] to do so. [[File:new_project_default_part.png|thumbnail|center]]
Choose the Zybo board, click next, and finish.

The project has now been created and ready for IP-block integration.
Click on "Create Block Design" in the left of the window. Give the design a name, for instance design_1, and click "OK".[[File:create_block_design.png|thumbnail|center]]

Now press the "+" button in the diagram window, and search for "ZYNQ7 Processing System". Double click to add. In the top of the window an option to "Run Block Automation" appears.. Click this, and complete with default settings. The window should now look like this: [[File:first_block.png|thumbnail|center]]

Goto: ''Tools -> Create and Package New IP''. Choose "Create a New AXI4 peripheral", and click next.
Name the IP "axi4_lite_led_IP" or any other suiting name. You can leave all other parameters default.
In the next window, ensure the IP contains one slave interface named S00_AXI of type "Lite". Click next, and choose "Add IP to the repository". Finish.[[File:add_interfaces_axi4lite.png|thumbnail|center]]

In the diagram window it's now possible to add the IP we just created, using the "+" button. Search for "axi4_lite_led_IP_v1.0" and add it. Run connection/block automation with default parameters.

[[File:diagram_axi4lite_periph_added.png|center]] 

Right click on "design_1" under "Block Designs" in the Sources design tree. Click "Create HDL Wrapper", and let Vivado manage wrapper and auto-update.

''Right click axi4_lite_led_IP_0 block --> Edit in IP Packager''. Then do the following edits to axi4_lite_led_IP_v1_0_S00_AXI.vhd and axi4_lite_led_IP_v1_0.vhd 
 

[[File:led_ip_1.png|400px]]
[[File:led_ip_2.png|400px]]
[[File:led_ip_3.png|400px]]
[[File:S00_1.png|400px]]
[[File:S00_2.png|400px]]

Save both files, and go into the "Ports and interfaces" tab. Click "Merge changes from Ports and Interfaces Wizard". A new port should now be listed named "led_port". Click on "Review and Package", and click Re-Package IP. Click yes on prompt to close project.

Click on "IP Status" tab, and choose "Upgrade Selected" if you are not automatically prompted. Go back to the Block design diagram, and right-click on the newly created port named "led_port[3:0]" on our custom IP and choose "make external". Save.

Open the constraints file ZYBO_Master.xdc located under Constraints in the sources tab design tree.
To avoid tons of warnings, comment out everything except from the 4 lines under "##LEDs".
Rewrite them to the following: 

set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led_port[3] }]; 
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led_port[2] }]; 
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led_port[1] }]; 
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led_port[0] }]; 

Save the file, and click "Generate Bitstream". Accept the launch of synthesis and implementation.
When complete, you can choose to open the implemented design and have a look at it, or specify timing restraints.

= Exporting Bitstream =

Goto: ''File --> Export --> Export Hardware'', and choose to include bitstream.

You are now done with this tutorial.

Running FreeRTOS on Xilinx Zybo

2017-12-06T12:25:12Z

Yag005: Created page with "Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS. This tutorial assumes you have completed the "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"-..."

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.

This tutorial assumes you have completed the "[[Creating example project with AXI4 Lite peripheral in Xilinx Vivado]]"-tutorial.

FreeRTOS FSBL

2017-12-06T12:25:05Z

Yag005:

Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS.

This tutorial assumes you have completed the "[[Running FreeRTOS on Xilinx Zybo]]"-tutorial.

===== Exporting hardware bitstream =====

After the bitstream was generated in the previous tutorial, it is now possible to export it.
''Goto: File -> Export -> Export Hardware..''
Make sure to include bitstream, and press "OK".
[[File:export_hardware.png|thumbnail|center]]

Next, goto: ''File -> Launch SDK''. The following window will appear:
[[File:Launch SDK.png|thumbnail|center]]
Press "OK" and wait for Xilinx SDK to start up and finish loading.

... Work in progress ...

FreeRTOS

2017-12-06T12:23:26Z

Yag005:

[[Running FreeRTOS on Xilinx Zybo]] - How to get FreeRTOS to run on the Xilinx Zybo SoC. 
[[FreeRTOS FSBL]] - First Stage Bootloader: Run FreeRTOS by booting OS and application project from SD-card.

FreeRTOS

2017-12-06T12:23:12Z

Yag005:

[[Running FreeRTOS on Xilinx Zybo]] - How to get FreeRTOS to run on the Xilinx Zybo SoC.
[[FreeRTOS FSBL]] - First Stage Bootloader: Run FreeRTOS by booting OS and application project from SD-card.

Creating example project with AXI4 Lite peripheral in Xilinx Vivado

2017-12-04T18:11:22Z

Yag005:

Creating example project with AXI4 Lite peripheral in Xilinx Vivado

2017-12-04T17:02:26Z

Yag005:

Creating example project with AXI4 Lite peripheral in Xilinx Vivado

2017-12-04T17:01:45Z

Yag005:

Tested on Xilinx Vivado 2017.3, using the Xilinx Digilent Zybo SoC.

Start ./vivado from installed directory.
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]

Do not add any sources, but make sure that both target and simulator language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.
Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub]. Make sure that the option to copy the constraints file(s) into the project is marked.

For the next step, the board files for the board we're using must have been installed. If this is not the case, follow [https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 this tutorial] to do so. [[File:new_project_default_part.png|thumbnail|center]]
Choose the Zybo board, click next, and finish.

The project has now been created and ready for IP-block integration.
Click on "Create Block Design" in the left of the window. Give the design a name, for instance design_1, and click "OK".[[File:create_block_design.png|thumbnail|center]]

Now press the "+" button in the diagram window, and search for "ZYNQ7 Processing System". Double click to add. In the top of the window an option to "Run Block Automation" appears.. Click this, and complete with default settings. The window should now look like this: [[File:first_block.png|thumbnail|center]]

Goto: ''Tools -> Create and Package New IP''. Choose "Create a New AXI4 peripheral", and click next.
Name the IP "axi4_lite_led_IP" or any other suiting name. You can leave all other parameters default.
In the next window, ensure the IP contains one slave interface named S00_AXI of type "Lite". Click next, and choose "Add IP to the repository". Finish.[[File:add_interfaces_axi4lite.png|thumbnail|center]]

In the diagram window it's now possible to add the IP we just created, using the "+" button. Search for "axi4_lite_led_IP_v1.0" and add it. Run connection/block automation with default parameters.

[[File:diagram_axi4lite_periph_added.png|center]] 

Right click on "design_1" under "Block Designs" in the Sources design tree. Click "Create HDL Wrapper", and let Vivado manage wrapper and auto-update.

''Right click axi4_lite_led_IP_0 block --> Edit in IP Packager''. Then do the following edits to axi4_lite_led_IP_v1_0_S00_AXI.vhd and axi4_lite_led_IP_v1_0.vhd 
 

[[File:led_ip_1.png|400px]]
[[File:led_ip_2.png|400px]]
[[File:led_ip_3.png|400px]]
[[File:S00_1.png|400px]]
[[File:S00_2.png|400px]]

Save both files, and go into the "Ports and interfaces" tab. Click "Merge changes from Ports and Interfaces Wizard". A new port should now be listed named "led_port". Click on "Review and Package", and click Re-Package IP. Click yes on prompt to close project.

Click on "IP Status" tab, and choose "Upgrade Selected" if you are not automatically prompted. Go back to the Block design diagram, and right-click on the newly created port named "led_port[3:0]" on our custom IP and choose "make external". Save.

Open the constraints file ZYBO_Master.xdc located under Constraints in the sources tab design tree.
To avoid tons of warnings, comment out everything except from the 4 lines under "##LEDs".
Rewrite them to the following: 

set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led_port[3] }]; #IO_L23P_T3_35 Sch=LED0 
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led_port[2] }]; #IO_L23N_T3_35 Sch=LED1 
set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led_port[1] }]; #IO_0_35=Sch=LED2 
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { led_port[0] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3

File:Led port success.png

2017-12-04T16:52:36Z

Yag005: Yag005 uploaded a new version of File:Led port success.png

File uploaded with MsUpload

Creating example project with AXI4 Lite peripheral in Xilinx Vivado

2017-12-04T16:52:01Z

Yag005:

Tested on Xilinx Vivado 2017.3, using the Xilinx Digilent Zybo SoC.

Start ./vivado from installed directory.
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]

Do not add any sources, but make sure that both target and simulator language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.
Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub]. Make sure that the option to copy the constraints file(s) into the project is marked.

For the next step, the board files for the board we're using must have been installed. If this is not the case, follow [https://reference.digilentinc.com/reference/software/vivado/board-files?redirect=1 this tutorial] to do so. [[File:new_project_default_part.png|thumbnail|center]]
Choose the Zybo board, click next, and finish.

The project has now been created and ready for IP-block integration.
Click on "Create Block Design" in the left of the window. Give the design a name, for instance design_1, and click "OK".[[File:create_block_design.png|thumbnail|center]]

Now press the "+" button in the diagram window, and search for "ZYNQ7 Processing System". Double click to add. In the top of the window an option to "Run Block Automation" appears.. Click this, and complete with default settings. The window should now look like this: [[File:first_block.png|thumbnail|center]]

Goto: ''Tools -> Create and Package New IP''. Choose "Create a New AXI4 peripheral", and click next.
Name the IP "axi4_lite_led_IP" or any other suiting name. You can leave all other parameters default.
In the next window, ensure the IP contains one slave interface named S00_AXI of type "Lite". Click next, and choose "Add IP to the repository". Finish.[[File:add_interfaces_axi4lite.png|thumbnail|center]]

In the diagram window it's now possible to add the IP we just created, using the "+" button. Search for "axi4_lite_led_IP_v1.0" and add it. Run connection/block automation with default parameters.

[[File:diagram_axi4lite_periph_added.png|center]] 

Right click on "design_1" under "Block Designs" in the Sources design tree. Click "Create HDL Wrapper", and let Vivado manage wrapper and auto-update.

''Right click axi4_lite_led_IP_0 block --> Edit in IP Packager''. Then do the following edits to axi4_lite_led_IP_v1_0_S00_AXI.vhd and axi4_lite_led_IP_v1_0.vhd 
 

[[File:led_ip_1.png|400px]]
[[File:led_ip_2.png|400px]]
[[File:led_ip_3.png|400px]]
[[File:S00_1.png|400px]]
[[File:S00_2.png|400px]]
[[File:led_port_success.png|400px]]

Save both files, and go into the "Ports and interfaces" tab. Click "Merge changes from Ports and Interfaces Wizard". A new port should now be listed named "led_port". Click on "Review and Package", and click Re-Package IP. Click yes on prompt to close project.

Click on "IP Status" tab, and choose "Upgrade Selected" if you are not automatically prompted.