ift - User contributions [en]

Microelectronics group

2009-06-05T13:27:24Z

St12361:

== Mikroelektronikk ==

Dokumentasjon for Mentor Graphics IC-programvaren finnes i katalogen /prog/mentor/mgc/ic.2006.2b/2006.2b_rhelx86linux/icflow_home/shared/pdfdocs eller ../htmldocs/

* [[IC studio]] Veiledning til IC-design ved hjelp av IC studio

* [[IC Station]] Tegne utlegg for integrerte kretser

* [[Expedition PCB]] Komme i gang med kretskortutlegg ved hjelp av Expedition PCB

* [[Modelsim/Questa]] Skrive og simulere VHDL-kode med Mentor Graphics ModelSim

* [[PCI-eksperiment]] Øving med HLT-RORC-prototypekort

* [[Cadence Virtuoso]]

* [[Xilinx]] Øving i bruk av Xilinx Project Studio

* [[FLTK GUI]] Graphical User Interface using FLTK

* [[Tutorials]] Tutorials from the web

* [[ADS]] Getting started with Agilent Advanced Design System

* [[PHYS321]] Øvingsoppgaver i PHYS321

[[Category:Mikroelektronikk]]

Demo.Net

2009-06-05T13:26:38Z

St12361: Created page with '.HEA .APP "Cadstar RINF Output - Version 2.3" .UNI INCH 1000.0 in .TYP FULL .JOB "XJTAGDEMOV3" .ADD_COM C1 "0805" .ATT_COM C1 "Supplier" "RE" .ATT_COM C1 "PCB Footprint" "0805"...'

.HEA
.APP "Cadstar RINF Output - Version 2.3"
.UNI INCH 1000.0 in
.TYP FULL
.JOB "XJTAGDEMOV3"

.ADD_COM C1 "0805"
.ATT_COM C1 "Supplier" "RE"
.ATT_COM C1 "PCB Footprint" "0805"
.ATT_COM C1 "timestamp" "000CFE8C"
.ATT_COM C1 "Type" "Y5V 50V"
.ATT_COM C1 "Source Package" "CAP NP"
.ATT_COM C1 "Order Code" "71-1400"
.ATT_COM C1 "Value" "100nF"
.ADD_COM C10 "0805"
.ATT_COM C10 "Supplier" "RE"
.ATT_COM C10 "PCB Footprint" "0805"
.ATT_COM C10 "timestamp" "000C1A25"
.ATT_COM C10 "Type" "Y5V 50V"
.ATT_COM C10 "Source Package" "CAP NP"
.ATT_COM C10 "Order Code" "71-1395"
.ATT_COM C10 "Value" "47nF"
.ADD_COM C11 "0805"
.ATT_COM C11 "Supplier" "RE"
.ATT_COM C11 "PCB Footprint" "0805"
.ATT_COM C11 "timestamp" "000C1A3D"
.ATT_COM C11 "Type" "Y5V 50V"
.ATT_COM C11 "Source Package" "CAP NP"
.ATT_COM C11 "Order Code" "71-1395"
.ATT_COM C11 "Value" "47nF"
.ADD_COM C2 "0805"
.ATT_COM C2 "Supplier" "RE"
.ATT_COM C2 "PCB Footprint" "0805"
.ATT_COM C2 "timestamp" "000CFC8A"
.ATT_COM C2 "Type" "Y5V 50V"
.ATT_COM C2 "Source Package" "CAP NP"
.ATT_COM C2 "Order Code" "71-1395"
.ATT_COM C2 "Value" "47nF"
.ADD_COM C3 "2.5mm pitch 6.3mmdia"
.ATT_COM C3 "Cost100" ".14"
.ATT_COM C3 "Supplier" "Newsham"
.ATT_COM C3 "PCB Footprint" "2.5mm pitch 6.3mmdia"
.ATT_COM C3 "Cost1" "0.16"
.ATT_COM C3 "timestamp" "0007DF6F"
.ATT_COM C3 "Type" "Low ESR"
.ATT_COM C3 "Source Package" "CAPACITOR POL"
.ATT_COM C3 "Manu" "Rubycon"
.ATT_COM C3 "Order Code" "768-080"
.ATT_COM C3 "Value" "220uF10v"
.ATT_COM C3 "Cost25" ".16"
.ATT_COM C3 "Man Ref" "10ZL220M6.3X11"
.ADD_COM C4 "0805"
.ATT_COM C4 "Supplier" "RE"
.ATT_COM C4 "PCB Footprint" "0805"
.ATT_COM C4 "timestamp" "0007643A"
.ATT_COM C4 "Type" "Y5V 50V"
.ATT_COM C4 "Source Package" "CAP NP"
.ATT_COM C4 "Order Code" "71-1395"
.ATT_COM C4 "Value" "47nF"
.ADD_COM C5 "0805"
.ATT_COM C5 "Supplier" "RE"
.ATT_COM C5 "PCB Footprint" "0805"
.ATT_COM C5 "timestamp" "000311A9"
.ATT_COM C5 "Type" "Y5V 50V"
.ATT_COM C5 "Source Package" "CAP NP"
.ATT_COM C5 "Order Code" "71-1395"
.ATT_COM C5 "Value" "47nF"
.ADD_COM C6 "0805"
.ATT_COM C6 "Supplier" "RE"
.ATT_COM C6 "PCB Footprint" "0805"
.ATT_COM C6 "timestamp" "000311C1"
.ATT_COM C6 "Type" "Y5V 50V"
.ATT_COM C6 "Source Package" "CAP NP"
.ATT_COM C6 "Order Code" "71-1395"
.ATT_COM C6 "Value" "47nF"
.ADD_COM C7 "0805"
.ATT_COM C7 "Supplier" "RE"
.ATT_COM C7 "PCB Footprint" "0805"
.ATT_COM C7 "timestamp" "0002B06B"
.ATT_COM C7 "Type" "Y5V 50V"
.ATT_COM C7 "Source Package" "CAP NP"
.ATT_COM C7 "Order Code" "71-1395"
.ATT_COM C7 "Value" "47nF"
.ADD_COM C8 "0805"
.ATT_COM C8 "Supplier" "RE"
.ATT_COM C8 "PCB Footprint" "0805"
.ATT_COM C8 "timestamp" "0002B0FB"
.ATT_COM C8 "Type" "Y5V 50V"
.ATT_COM C8 "Source Package" "CAP NP"
.ATT_COM C8 "Order Code" "71-1395"
.ATT_COM C8 "Value" "47nF"
.ADD_COM C9 "0805"
.ATT_COM C9 "Supplier" "RE"
.ATT_COM C9 "PCB Footprint" "0805"
.ATT_COM C9 "timestamp" "0002B0C3"
.ATT_COM C9 "Type" "Y5V 50V"
.ATT_COM C9 "Source Package" "CAP NP"
.ATT_COM C9 "Order Code" "71-1395"
.ATT_COM C9 "Value" "47nF"
.ADD_COM CN1 "20 Way RA Box header socket"
.ATT_COM CN1 "Cost100" "0.695"
.ATT_COM CN1 "Supplier" "RE"
.ATT_COM CN1 "Cost1" "0.85"
.ATT_COM CN1 "PCB Footprint" "20 Way RA Box header socket"
.ATT_COM CN1 "timestamp" "0007EBB1"
.ATT_COM CN1 "Source Package" "CON20A"
.ATT_COM CN1 "Order Code" "22-4140"
.ATT_COM CN1 "Value" "CON20A"
.ADD_COM CN2 "2x2.54mm holes"
.ATT_COM CN2 "Fitted" "nf"
.ATT_COM CN2 "PCB Footprint" "2x2.54mm holes"
.ATT_COM CN2 "timestamp" "000D429A"
.ATT_COM CN2 "Source Package" "CON2"
.ATT_COM CN2 "Value" "2pin"
.ADD_COM CN3 "20way DIL"
.ATT_COM CN3 "Cost100" "0.065"
.ATT_COM CN3 "Supplier" "RE"
.ATT_COM CN3 "Cost1" "0.11"
.ATT_COM CN3 "PCB Footprint" "20way DIL"
.ATT_COM CN3 "timestamp" "000C9077"
.ATT_COM CN3 "Cost50" "0.07"
.ATT_COM CN3 "Source Package" "DIL socket20way"
.ATT_COM CN3 "Order Code" "22-0170"
.ATT_COM CN3 "Value" "DIL socket20way"
.ADD_COM D1 "SOT23"
.ATT_COM D1 "Cost100" "0.11"
.ATT_COM D1 "Supplier" "RE"
.ATT_COM D1 "PCB Footprint" "SOT23"
.ATT_COM D1 "timestamp" "000CC264"
.ATT_COM D1 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D1 "Cost10" "0.15"
.ATT_COM D1 "Manu" "KingBright"
.ATT_COM D1 "Order Code" "72-8795"
.ATT_COM D1 "Value" "Red/Green"
.ATT_COM D1 "Man Ref" "KM23 series"
.ADD_COM D2 "SOT23"
.ATT_COM D2 "Cost100" "0.11"
.ATT_COM D2 "Supplier" "RE"
.ATT_COM D2 "PCB Footprint" "SOT23"
.ATT_COM D2 "timestamp" "000CC122"
.ATT_COM D2 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D2 "Cost10" "0.15"
.ATT_COM D2 "Manu" "KingBright"
.ATT_COM D2 "Order Code" "72-8795"
.ATT_COM D2 "Value" "Red/Green"
.ATT_COM D2 "Man Ref" "KM23 series"
.ADD_COM D3 "SOT23"
.ATT_COM D3 "Cost100" "0.11"
.ATT_COM D3 "Supplier" "RE"
.ATT_COM D3 "PCB Footprint" "SOT23"
.ATT_COM D3 "timestamp" "000CBFE0"
.ATT_COM D3 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D3 "Cost10" "0.15"
.ATT_COM D3 "Manu" "KingBright"
.ATT_COM D3 "Order Code" "72-8795"
.ATT_COM D3 "Value" "Red/Green"
.ATT_COM D3 "Man Ref" "KM23 series"
.ADD_COM D4 "SOT23"
.ATT_COM D4 "Cost100" "0.11"
.ATT_COM D4 "Supplier" "RE"
.ATT_COM D4 "PCB Footprint" "SOT23"
.ATT_COM D4 "timestamp" "000CC340"
.ATT_COM D4 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D4 "Cost10" "0.15"
.ATT_COM D4 "Manu" "KingBright"
.ATT_COM D4 "Order Code" "72-8795"
.ATT_COM D4 "Value" "Red/Green"
.ATT_COM D4 "Man Ref" "KM23 series"
.ADD_COM D5 "SOT23"
.ATT_COM D5 "Cost100" "0.11"
.ATT_COM D5 "Supplier" "RE"
.ATT_COM D5 "PCB Footprint" "SOT23"
.ATT_COM D5 "timestamp" "000CC1FE"
.ATT_COM D5 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D5 "Cost10" "0.15"
.ATT_COM D5 "Manu" "KingBright"
.ATT_COM D5 "Order Code" "72-8795"
.ATT_COM D5 "Value" "Red/Green"
.ATT_COM D5 "Man Ref" "KM23 series"
.ADD_COM D6 "SOT23"
.ATT_COM D6 "Cost100" "0.11"
.ATT_COM D6 "Supplier" "RE"
.ATT_COM D6 "PCB Footprint" "SOT23"
.ATT_COM D6 "timestamp" "000CC0BC"
.ATT_COM D6 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D6 "Cost10" "0.15"
.ATT_COM D6 "Manu" "KingBright"
.ATT_COM D6 "Order Code" "72-8795"
.ATT_COM D6 "Value" "Red/Green"
.ATT_COM D6 "Man Ref" "KM23 series"
.ADD_COM D7 "SOT23"
.ATT_COM D7 "Cost100" "0.11"
.ATT_COM D7 "Supplier" "RE"
.ATT_COM D7 "PCB Footprint" "SOT23"
.ATT_COM D7 "timestamp" "000CC2BC"
.ATT_COM D7 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D7 "Cost10" "0.15"
.ATT_COM D7 "Manu" "KingBright"
.ATT_COM D7 "Order Code" "72-8795"
.ATT_COM D7 "Value" "Red/Green"
.ATT_COM D7 "Man Ref" "KM23 series"
.ADD_COM D8 "SOT23"
.ATT_COM D8 "Cost100" "0.11"
.ATT_COM D8 "Supplier" "RE"
.ATT_COM D8 "PCB Footprint" "SOT23"
.ATT_COM D8 "timestamp" "000CC17A"
.ATT_COM D8 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D8 "Cost10" "0.15"
.ATT_COM D8 "Manu" "KingBright"
.ATT_COM D8 "Order Code" "72-8795"
.ATT_COM D8 "Value" "Red/Green"
.ATT_COM D8 "Man Ref" "KM23 series"
.ADD_COM D9 "SOT23"
.ATT_COM D9 "Cost100" "0.11"
.ATT_COM D9 "Supplier" "RE"
.ATT_COM D9 "PCB Footprint" "SOT23"
.ATT_COM D9 "timestamp" "000CC038"
.ATT_COM D9 "Source Package" "LED BI-COLOUR_0"
.ATT_COM D9 "Cost10" "0.15"
.ATT_COM D9 "Manu" "KingBright"
.ATT_COM D9 "Order Code" "72-8795"
.ATT_COM D9 "Value" "Red/Green"
.ATT_COM D9 "Man Ref" "KM23 series"
.ADD_COM IC1 "SO14"
.ATT_COM IC1 "Supplier" "FEC"
.ATT_COM IC1 "PCB Footprint" "SO14"
.ATT_COM IC1 "timestamp" "000CFAD0"
.ATT_COM IC1 "Source Package" "74HC04/SO"
.ATT_COM IC1 "Order Code" "379-268"
.ATT_COM IC1 "Value" "74HC14"
.ADD_COM IC2 "CS48"
.ATT_COM IC2 "Supplier" "Insight"
.ATT_COM IC2 "PCB Footprint" "CS48"
.ATT_COM IC2 "Cost1" "$0.99"
.ATT_COM IC2 "timestamp" "000C8277"
.ATT_COM IC2 "Source Package" "XC9536/VFP_1"
.ATT_COM IC2 "Manu" "Xilinx"
.ATT_COM IC2 "Man ref" "XC9536XL-10CS48C"
.ATT_COM IC2 "Value" "XC9536XL"
.ADD_COM IC3 "44 TQFP"
.ATT_COM IC3 "Supplier" "Unique"
.ATT_COM IC3 "PCB Footprint" "44 TQFP"
.ATT_COM IC3 "timestamp" "000C89EA"
.ATT_COM IC3 "Source Package" "EPM3032A"
.ATT_COM IC3 "Value" "EPM3032A"
.ADD_COM IC4 "SO8"
.ATT_COM IC4 "Cost100" "0.45"
.ATT_COM IC4 "Supplier" "FEC"
.ATT_COM IC4 "PCB Footprint" "SO8"
.ATT_COM IC4 "Cost1" "0.65"
.ATT_COM IC4 "timestamp" "000854DF"
.ATT_COM IC4 "Source Package" "24LC01B/SO"
.ATT_COM IC4 "Manu" "Microchip"
.ATT_COM IC4 "Cost10" "0.53"
.ATT_COM IC4 "Order Code" "300-1647"
.ATT_COM IC4 "Value" "24LC32A"
.ATT_COM IC4 "Man Ref" "24LC32A/SN"
.ADD_COM IC5 "SMT 24"
.ATT_COM IC5 "Cost100" "0.8"
.ATT_COM IC5 "Supplier" "FEC"
.ATT_COM IC5 "PCB Footprint" "SMT 24"
.ATT_COM IC5 "Cost1" "1.26"
.ATT_COM IC5 "timestamp" "000C9105"
.ATT_COM IC5 "Source Package" "HM6116"
.ATT_COM IC5 "Manu" "HT"
.ATT_COM IC5 "Cost10" ".96"
.ATT_COM IC5 "Order Code" "115-861"
.ATT_COM IC5 "Value" "HT6116"
.ATT_COM IC5 "Man Ref" "HT6116-70S"
.ADD_COM JP1 "4x2x2.54mm Holes"
.ATT_COM JP1 "Cost100" "0.04"
.ATT_COM JP1 "Supplier" "RE"
.ATT_COM JP1 "PCB Footprint" "4x2x2.54mm Holes"
.ATT_COM JP1 "Cost1" "0.06"
.ATT_COM JP1 "timestamp" "000D3012"
.ATT_COM JP1 "Source Package" "JUMPER4"
.ATT_COM JP1 "Order Code" "22-0555"
.ATT_COM JP1 "Value" "JUMPER4"
.ADD_COM JP2 "4x2x2.54mm Holes"
.ATT_COM JP2 "Cost100" "0.04"
.ATT_COM JP2 "Supplier" "RE"
.ATT_COM JP2 "PCB Footprint" "4x2x2.54mm Holes"
.ATT_COM JP2 "Cost1" "0.06"
.ATT_COM JP2 "timestamp" "000D3162"
.ATT_COM JP2 "Source Package" "JUMPER4"
.ATT_COM JP2 "Order Code" "22-0555"
.ATT_COM JP2 "Value" "JUMPER4"
.ADD_COM JP3 "4x2x2.54mm Holes"
.ATT_COM JP3 "Cost100" "0.04"
.ATT_COM JP3 "Supplier" "RE"
.ATT_COM JP3 "PCB Footprint" "4x2x2.54mm Holes"
.ATT_COM JP3 "Cost1" "0.06"
.ATT_COM JP3 "timestamp" "000D2B1D"
.ATT_COM JP3 "Source Package" "JUMPER4"
.ATT_COM JP3 "Order Code" "22-0555"
.ATT_COM JP3 "Value" "JUMPER4"
.ADD_COM JP4 "10x1x2.54mm holes"
.ATT_COM JP4 "Cost100" "0.04"
.ATT_COM JP4 "Supplier" "RE"
.ATT_COM JP4 "Cost1" "0.006"
.ATT_COM JP4 "PCB Footprint" "10x1x2.54mm holes"
.ATT_COM JP4 "timestamp" "000C97FA"
.ATT_COM JP4 "Source Package" "JUMPER10_0"
.ATT_COM JP4 "Order Code" "22-0515"
.ATT_COM JP4 "Value" "JUMPhalf"
.ADD_COM JP5 "10x2x 2.54mm holes"
.ATT_COM JP5 "Cost100" "0.08"
.ATT_COM JP5 "Supplier" "RE"
.ATT_COM JP5 "Cost1" "0.12"
.ATT_COM JP5 "PCB Footprint" "10x2x 2.54mm holes"
.ATT_COM JP5 "timestamp" "000C95CE"
.ATT_COM JP5 "Source Package" "JUMPER10"
.ATT_COM JP5 "Order Code" "22-0565"
.ATT_COM JP5 "Value" "JUMPER10"
.ADD_COM JP6 "10x2x 2.54mm holes"
.ATT_COM JP6 "Cost100" "0.08"
.ATT_COM JP6 "Supplier" "RE"
.ATT_COM JP6 "Cost1" "0.12"
.ATT_COM JP6 "PCB Footprint" "10x2x 2.54mm holes"
.ATT_COM JP6 "timestamp" "000C9EF3"
.ATT_COM JP6 "Source Package" "JUMPER10"
.ATT_COM JP6 "Order Code" "22-0565"
.ATT_COM JP6 "Value" "JUMPER10"
.ADD_COM JP7 "10x1x2.54mm holes"
.ATT_COM JP7 "Cost100" "0.04"
.ATT_COM JP7 "Supplier" "RE"
.ATT_COM JP7 "Cost1" "0.006"
.ATT_COM JP7 "PCB Footprint" "10x1x2.54mm holes"
.ATT_COM JP7 "timestamp" "000CA363"
.ATT_COM JP7 "Source Package" "JUMPER10_0"
.ATT_COM JP7 "Order Code" "22-0515"
.ATT_COM JP7 "Value" "JUMPhalf"
.ADD_COM R1 "0805"
.ATT_COM R1 "Cost100" "0.006"
.ATT_COM R1 "Supplier" "RE"
.ATT_COM R1 "PCB Footprint" "0805"
.ATT_COM R1 "Cost1" "0.023"
.ATT_COM R1 "timestamp" "000CFEB8"
.ATT_COM R1 "Cost1000" "0.00710"
.ATT_COM R1 "Pack" "100"
.ATT_COM R1 "Source Package" "R"
.ATT_COM R1 "Order Code" "72-0442"
.ATT_COM R1 "Value" "10M"
.ATT_COM R1 "Cost25" "0.023"
.ADD_COM R10 "0805"
.ATT_COM R10 "Cost100" "0.006"
.ATT_COM R10 "Supplier" "RE"
.ATT_COM R10 "PCB Footprint" "0805"
.ATT_COM R10 "Cost1" "0.023"
.ATT_COM R10 "timestamp" "000CC1DA"
.ATT_COM R10 "Cost1000" "0.00710"
.ATT_COM R10 "Pack" "100"
.ATT_COM R10 "Source Package" "R"
.ATT_COM R10 "Order Code" "72-4392"
.ATT_COM R10 "Value" "120R"
.ATT_COM R10 "Cost25" "0.023"
.ADD_COM R11 "0805"
.ATT_COM R11 "Cost100" "0.006"
.ATT_COM R11 "Supplier" "RE"
.ATT_COM R11 "PCB Footprint" "0805"
.ATT_COM R11 "Cost1" "0.023"
.ATT_COM R11 "timestamp" "000CC098"
.ATT_COM R11 "Cost1000" "0.00710"
.ATT_COM R11 "Pack" "100"
.ATT_COM R11 "Source Package" "R"
.ATT_COM R11 "Order Code" "72-4392"
.ATT_COM R11 "Value" "120R"
.ATT_COM R11 "Cost25" "0.023"
.ADD_COM R12 "0805"
.ATT_COM R12 "Cost100" "0.006"
.ATT_COM R12 "Supplier" "RE"
.ATT_COM R12 "PCB Footprint" "0805"
.ATT_COM R12 "timestamp" "000DAEC9"
.ATT_COM R12 "Pack" "100"
.ATT_COM R12 "Source Package" "R"
.ATT_COM R12 "Value" "8.2K"
.ADD_COM R13 "0805"
.ATT_COM R13 "Cost100" "0.006"
.ATT_COM R13 "Supplier" "RE"
.ATT_COM R13 "PCB Footprint" "0805"
.ATT_COM R13 "timestamp" "000DAFE7"
.ATT_COM R13 "Pack" "100"
.ATT_COM R13 "Source Package" "R"
.ATT_COM R13 "Value" "8.2K"
.ADD_COM R14 "0805"
.ATT_COM R14 "Cost100" "0.006"
.ATT_COM R14 "Supplier" "RE"
.ATT_COM R14 "PCB Footprint" "0805"
.ATT_COM R14 "Cost1" "0.023"
.ATT_COM R14 "timestamp" "000CC2A0"
.ATT_COM R14 "Cost1000" "0.00710"
.ATT_COM R14 "Pack" "100"
.ATT_COM R14 "Source Package" "R"
.ATT_COM R14 "Order Code" "72-4392"
.ATT_COM R14 "Value" "120R"
.ATT_COM R14 "Cost25" "0.023"
.ADD_COM R15 "0805"
.ATT_COM R15 "Cost100" "0.006"
.ATT_COM R15 "Supplier" "RE"
.ATT_COM R15 "PCB Footprint" "0805"
.ATT_COM R15 "Cost1" "0.023"
.ATT_COM R15 "timestamp" "000CC15E"
.ATT_COM R15 "Cost1000" "0.00710"
.ATT_COM R15 "Pack" "100"
.ATT_COM R15 "Source Package" "R"
.ATT_COM R15 "Order Code" "72-4392"
.ATT_COM R15 "Value" "120R"
.ATT_COM R15 "Cost25" "0.023"
.ADD_COM R16 "0805"
.ATT_COM R16 "Cost100" "0.006"
.ATT_COM R16 "Supplier" "RE"
.ATT_COM R16 "PCB Footprint" "0805"
.ATT_COM R16 "Cost1" "0.023"
.ATT_COM R16 "timestamp" "000CC01C"
.ATT_COM R16 "Cost1000" "0.00710"
.ATT_COM R16 "Pack" "100"
.ATT_COM R16 "Source Package" "R"
.ATT_COM R16 "Order Code" "72-4392"
.ATT_COM R16 "Value" "120R"
.ATT_COM R16 "Cost25" "0.023"
.ADD_COM R17 "0805"
.ATT_COM R17 "Cost100" "0.006"
.ATT_COM R17 "Supplier" "RE"
.ATT_COM R17 "PCB Footprint" "0805"
.ATT_COM R17 "Cost1" "0.023"
.ATT_COM R17 "timestamp" "000CC284"
.ATT_COM R17 "Cost1000" "0.00710"
.ATT_COM R17 "Pack" "100"
.ATT_COM R17 "Source Package" "R"
.ATT_COM R17 "Order Code" "72-4392"
.ATT_COM R17 "Value" "120R"
.ATT_COM R17 "Cost25" "0.023"
.ADD_COM R18 "0805"
.ATT_COM R18 "Cost100" "0.006"
.ATT_COM R18 "Supplier" "RE"
.ATT_COM R18 "PCB Footprint" "0805"
.ATT_COM R18 "Cost1" "0.023"
.ATT_COM R18 "timestamp" "000CC142"
.ATT_COM R18 "Cost1000" "0.00710"
.ATT_COM R18 "Pack" "100"
.ATT_COM R18 "Source Package" "R"
.ATT_COM R18 "Order Code" "72-4392"
.ATT_COM R18 "Value" "120R"
.ATT_COM R18 "Cost25" "0.023"
.ADD_COM R19 "0805"
.ATT_COM R19 "Cost100" "0.006"
.ATT_COM R19 "Supplier" "RE"
.ATT_COM R19 "PCB Footprint" "0805"
.ATT_COM R19 "Cost1" "0.023"
.ATT_COM R19 "timestamp" "000CC000"
.ATT_COM R19 "Cost1000" "0.00710"
.ATT_COM R19 "Pack" "100"
.ATT_COM R19 "Source Package" "R"
.ATT_COM R19 "Order Code" "72-4392"
.ATT_COM R19 "Value" "120R"
.ATT_COM R19 "Cost25" "0.023"
.ADD_COM R2 "0805"
.ATT_COM R2 "Cost100" "0.006"
.ATT_COM R2 "Supplier" "RE"
.ATT_COM R2 "PCB Footprint" "0805"
.ATT_COM R2 "Cost1" "0.023"
.ATT_COM R2 "timestamp" "000CFBEB"
.ATT_COM R2 "Cost1000" "0.00710"
.ATT_COM R2 "Pack" "100"
.ATT_COM R2 "Source Package" "R"
.ATT_COM R2 "Order Code" "72-0397"
.ATT_COM R2 "Value" "1M"
.ATT_COM R2 "Cost25" "0.023"
.ADD_COM R20 "0805"
.ATT_COM R20 "Cost100" "0.006"
.ATT_COM R20 "Supplier" "RE"
.ATT_COM R20 "PCB Footprint" "0805"
.ATT_COM R20 "Cost1" "0.023"
.ATT_COM R20 "timestamp" "000CC2F0"
.ATT_COM R20 "Cost1000" "0.00710"
.ATT_COM R20 "Pack" "100"
.ATT_COM R20 "Source Package" "R"
.ATT_COM R20 "Order Code" "72-4392"
.ATT_COM R20 "Value" "120R"
.ATT_COM R20 "Cost25" "0.023"
.ADD_COM R21 "0805"
.ATT_COM R21 "Cost100" "0.006"
.ATT_COM R21 "Supplier" "RE"
.ATT_COM R21 "PCB Footprint" "0805"
.ATT_COM R21 "Cost1" "0.023"
.ATT_COM R21 "timestamp" "000CC1AE"
.ATT_COM R21 "Cost1000" "0.00710"
.ATT_COM R21 "Pack" "100"
.ATT_COM R21 "Source Package" "R"
.ATT_COM R21 "Order Code" "72-4392"
.ATT_COM R21 "Value" "120R"
.ATT_COM R21 "Cost25" "0.023"
.ADD_COM R22 "0805"
.ATT_COM R22 "Cost100" "0.006"
.ATT_COM R22 "Supplier" "RE"
.ATT_COM R22 "PCB Footprint" "0805"
.ATT_COM R22 "Cost1" "0.023"
.ATT_COM R22 "timestamp" "000CC06C"
.ATT_COM R22 "Cost1000" "0.00710"
.ATT_COM R22 "Pack" "100"
.ATT_COM R22 "Source Package" "R"
.ATT_COM R22 "Order Code" "72-4392"
.ATT_COM R22 "Value" "120R"
.ATT_COM R22 "Cost25" "0.023"
.ADD_COM R23 "0805"
.ATT_COM R23 "Cost100" "0.006"
.ATT_COM R23 "Supplier" "RE"
.ATT_COM R23 "PCB Footprint" "0805"
.ATT_COM R23 "Cost1" "0.023"
.ATT_COM R23 "timestamp" "000CC23C"
.ATT_COM R23 "Cost1000" "0.00710"
.ATT_COM R23 "Pack" "100"
.ATT_COM R23 "Source Package" "R"
.ATT_COM R23 "Order Code" "72-4392"
.ATT_COM R23 "Value" "120R"
.ATT_COM R23 "Cost25" "0.023"
.ADD_COM R24 "0805"
.ATT_COM R24 "Cost100" "0.006"
.ATT_COM R24 "Supplier" "RE"
.ATT_COM R24 "PCB Footprint" "0805"
.ATT_COM R24 "Cost1" "0.023"
.ATT_COM R24 "timestamp" "000CC0FA"
.ATT_COM R24 "Cost1000" "0.00710"
.ATT_COM R24 "Pack" "100"
.ATT_COM R24 "Source Package" "R"
.ATT_COM R24 "Order Code" "72-4392"
.ATT_COM R24 "Value" "120R"
.ATT_COM R24 "Cost25" "0.023"
.ADD_COM R25 "0805"
.ATT_COM R25 "Cost100" "0.006"
.ATT_COM R25 "Supplier" "RE"
.ATT_COM R25 "PCB Footprint" "0805"
.ATT_COM R25 "Cost1" "0.023"
.ATT_COM R25 "timestamp" "000CBFB8"
.ATT_COM R25 "Cost1000" "0.00710"
.ATT_COM R25 "Pack" "100"
.ATT_COM R25 "Source Package" "R"
.ATT_COM R25 "Order Code" "72-4392"
.ATT_COM R25 "Value" "120R"
.ATT_COM R25 "Cost25" "0.023"
.ADD_COM R26 "0805"
.ATT_COM R26 "Cost100" "0.006"
.ATT_COM R26 "Supplier" "RE"
.ATT_COM R26 "PCB Footprint" "0805"
.ATT_COM R26 "Cost1" "0.023"
.ATT_COM R26 "timestamp" "000CC2D8"
.ATT_COM R26 "Cost1000" "0.00710"
.ATT_COM R26 "Pack" "100"
.ATT_COM R26 "Source Package" "R"
.ATT_COM R26 "Order Code" "72-4392"
.ATT_COM R26 "Value" "120R"
.ATT_COM R26 "Cost25" "0.023"
.ADD_COM R27 "0805"
.ATT_COM R27 "Cost100" "0.006"
.ATT_COM R27 "Supplier" "RE"
.ATT_COM R27 "PCB Footprint" "0805"
.ATT_COM R27 "Cost1" "0.023"
.ATT_COM R27 "timestamp" "000CC196"
.ATT_COM R27 "Cost1000" "0.00710"
.ATT_COM R27 "Pack" "100"
.ATT_COM R27 "Source Package" "R"
.ATT_COM R27 "Order Code" "72-4392"
.ATT_COM R27 "Value" "120R"
.ATT_COM R27 "Cost25" "0.023"
.ADD_COM R28 "0805"
.ATT_COM R28 "Cost100" "0.006"
.ATT_COM R28 "Supplier" "RE"
.ATT_COM R28 "PCB Footprint" "0805"
.ATT_COM R28 "Cost1" "0.023"
.ATT_COM R28 "timestamp" "000CC054"
.ATT_COM R28 "Cost1000" "0.00710"
.ATT_COM R28 "Pack" "100"
.ATT_COM R28 "Source Package" "R"
.ATT_COM R28 "Order Code" "72-4392"
.ATT_COM R28 "Value" "120R"
.ATT_COM R28 "Cost25" "0.023"
.ADD_COM R29 "0805"
.ATT_COM R29 "Cost100" "0.006"
.ATT_COM R29 "Supplier" "RE"
.ATT_COM R29 "PCB Footprint" "0805"
.ATT_COM R29 "timestamp" "000DAA80"
.ATT_COM R29 "Pack" "100"
.ATT_COM R29 "Source Package" "R"
.ATT_COM R29 "Value" "8.2K"
.ADD_COM R3 "0805"
.ATT_COM R3 "Cost100" "0.006"
.ATT_COM R3 "Supplier" "RE"
.ATT_COM R3 "PCB Footprint" "0805"
.ATT_COM R3 "timestamp" "000DADEB"
.ATT_COM R3 "Pack" "100"
.ATT_COM R3 "Source Package" "R"
.ATT_COM R3 "Value" "8.2K"
.ADD_COM R30 "0805"
.ATT_COM R30 "Cost100" "0.006"
.ATT_COM R30 "Supplier" "RE"
.ATT_COM R30 "PCB Footprint" "0805"
.ATT_COM R30 "timestamp" "000DB08F"
.ATT_COM R30 "Pack" "100"
.ATT_COM R30 "Source Package" "R"
.ATT_COM R30 "Value" "8.2K"
.ADD_COM R31 "0805"
.ATT_COM R31 "Cost100" "0.006"
.ATT_COM R31 "Supplier" "RE"
.ATT_COM R31 "PCB Footprint" "0805"
.ATT_COM R31 "timestamp" "000DB0BB"
.ATT_COM R31 "Pack" "100"
.ATT_COM R31 "Source Package" "R"
.ATT_COM R31 "Value" "8.2K"
.ADD_COM R32 "0805"
.ATT_COM R32 "Cost100" "0.006"
.ATT_COM R32 "Supplier" "RE"
.ATT_COM R32 "PCB Footprint" "0805"
.ATT_COM R32 "timestamp" "000DB0D3"
.ATT_COM R32 "Pack" "100"
.ATT_COM R32 "Source Package" "R"
.ATT_COM R32 "Value" "8.2K"
.ADD_COM R33 "0805"
.ATT_COM R33 "Cost100" "0.006"
.ATT_COM R33 "Supplier" "RE"
.ATT_COM R33 "PCB Footprint" "0805"
.ATT_COM R33 "timestamp" "000DB12B"
.ATT_COM R33 "Pack" "100"
.ATT_COM R33 "Source Package" "R"
.ATT_COM R33 "Value" "8.2K"
.ADD_COM R34 "0805"
.ATT_COM R34 "Cost100" "0.006"
.ATT_COM R34 "Supplier" "RE"
.ATT_COM R34 "PCB Footprint" "0805"
.ATT_COM R34 "timestamp" "000DB143"
.ATT_COM R34 "Pack" "100"
.ATT_COM R34 "Source Package" "R"
.ATT_COM R34 "Value" "8.2K"
.ADD_COM R35 "0805"
.ATT_COM R35 "Cost100" "0.006"
.ATT_COM R35 "Supplier" "RE"
.ATT_COM R35 "PCB Footprint" "0805"
.ATT_COM R35 "timestamp" "000DB15B"
.ATT_COM R35 "Pack" "100"
.ATT_COM R35 "Source Package" "R"
.ATT_COM R35 "Value" "8.2K"
.ADD_COM R36 "0805"
.ATT_COM R36 "Cost100" "0.006"
.ATT_COM R36 "Supplier" "RE"
.ATT_COM R36 "PCB Footprint" "0805"
.ATT_COM R36 "timestamp" "000DB173"
.ATT_COM R36 "Pack" "100"
.ATT_COM R36 "Source Package" "R"
.ATT_COM R36 "Value" "8.2K"
.ADD_COM R37 "0805"
.ATT_COM R37 "Cost100" "0.006"
.ATT_COM R37 "Supplier" "RE"
.ATT_COM R37 "PCB Footprint" "0805"
.ATT_COM R37 "timestamp" "000DB1DB"
.ATT_COM R37 "Pack" "100"
.ATT_COM R37 "Source Package" "R"
.ATT_COM R37 "Value" "8.2K"
.ADD_COM R38 "0805"
.ATT_COM R38 "Cost100" "0.006"
.ATT_COM R38 "Supplier" "RE"
.ATT_COM R38 "PCB Footprint" "0805"
.ATT_COM R38 "timestamp" "000DB1F3"
.ATT_COM R38 "Pack" "100"
.ATT_COM R38 "Source Package" "R"
.ATT_COM R38 "Value" "8.2K"
.ADD_COM R39 "0805"
.ATT_COM R39 "Cost100" "0.006"
.ATT_COM R39 "Supplier" "RE"
.ATT_COM R39 "PCB Footprint" "0805"
.ATT_COM R39 "timestamp" "000DB20B"
.ATT_COM R39 "Pack" "100"
.ATT_COM R39 "Source Package" "R"
.ATT_COM R39 "Value" "8.2K"
.ADD_COM R4 "0805"
.ATT_COM R4 "Cost100" "0.006"
.ATT_COM R4 "Supplier" "RE"
.ATT_COM R4 "PCB Footprint" "0805"
.ATT_COM R4 "timestamp" "000DACD7"
.ATT_COM R4 "Pack" "100"
.ATT_COM R4 "Source Package" "R"
.ATT_COM R4 "Value" "8.2K"
.ADD_COM R40 "0805"
.ATT_COM R40 "Cost100" "0.006"
.ATT_COM R40 "Supplier" "RE"
.ATT_COM R40 "PCB Footprint" "0805"
.ATT_COM R40 "timestamp" "000DB223"
.ATT_COM R40 "Pack" "100"
.ATT_COM R40 "Source Package" "R"
.ATT_COM R40 "Value" "8.2K"
.ADD_COM R41 "0805"
.ATT_COM R41 "Cost100" "0.006"
.ATT_COM R41 "Supplier" "RE"
.ATT_COM R41 "PCB Footprint" "0805"
.ATT_COM R41 "timestamp" "000DB23B"
.ATT_COM R41 "Pack" "100"
.ATT_COM R41 "Source Package" "R"
.ATT_COM R41 "Value" "8.2K"
.ADD_COM R42 "0805"
.ATT_COM R42 "Cost100" "0.006"
.ATT_COM R42 "Supplier" "RE"
.ATT_COM R42 "PCB Footprint" "0805"
.ATT_COM R42 "timestamp" "000DB253"
.ATT_COM R42 "Pack" "100"
.ATT_COM R42 "Source Package" "R"
.ATT_COM R42 "Value" "8.2K"
.ADD_COM R43 "0805"
.ATT_COM R43 "Cost100" "0.006"
.ATT_COM R43 "Supplier" "RE"
.ATT_COM R43 "PCB Footprint" "0805"
.ATT_COM R43 "timestamp" "000DB26B"
.ATT_COM R43 "Pack" "100"
.ATT_COM R43 "Source Package" "R"
.ATT_COM R43 "Value" "8.2K"
.ADD_COM R44 "0805"
.ATT_COM R44 "Cost100" "0.006"
.ATT_COM R44 "Supplier" "RE"
.ATT_COM R44 "PCB Footprint" "0805"
.ATT_COM R44 "timestamp" "000DB283"
.ATT_COM R44 "Pack" "100"
.ATT_COM R44 "Source Package" "R"
.ATT_COM R44 "Value" "8.2K"
.ADD_COM R45 "0805"
.ATT_COM R45 "Cost100" "0.006"
.ATT_COM R45 "Supplier" "RE"
.ATT_COM R45 "PCB Footprint" "0805"
.ATT_COM R45 "timestamp" "000DB80E"
.ATT_COM R45 "Pack" "100"
.ATT_COM R45 "Source Package" "R"
.ATT_COM R45 "Value" "8.2K"
.ADD_COM R46 "0805"
.ATT_COM R46 "Cost100" "0.006"
.ATT_COM R46 "Supplier" "RE"
.ATT_COM R46 "PCB Footprint" "0805"
.ATT_COM R46 "timestamp" "000DB826"
.ATT_COM R46 "Pack" "100"
.ATT_COM R46 "Source Package" "R"
.ATT_COM R46 "Value" "8.2K"
.ADD_COM R47 "0805"
.ATT_COM R47 "Cost100" "0.006"
.ATT_COM R47 "Supplier" "RE"
.ATT_COM R47 "PCB Footprint" "0805"
.ATT_COM R47 "timestamp" "000DB83E"
.ATT_COM R47 "Pack" "100"
.ATT_COM R47 "Source Package" "R"
.ATT_COM R47 "Value" "8.2K"
.ADD_COM R48 "0805"
.ATT_COM R48 "Cost100" "0.006"
.ATT_COM R48 "Supplier" "RE"
.ATT_COM R48 "PCB Footprint" "0805"
.ATT_COM R48 "timestamp" "000DB856"
.ATT_COM R48 "Pack" "100"
.ATT_COM R48 "Source Package" "R"
.ATT_COM R48 "Value" "8.2K"
.ADD_COM R49 "0805"
.ATT_COM R49 "Cost100" "0.006"
.ATT_COM R49 "Supplier" "RE"
.ATT_COM R49 "Cost1" "0.023"
.ATT_COM R49 "PCB Footprint" "0805"
.ATT_COM R49 "timestamp" "000DE221"
.ATT_COM R49 "Pack" "100"
.ATT_COM R49 "Cost1000" "0.00710"
.ATT_COM R49 "Source Package" "R"
.ATT_COM R49 "Order Code" "72-4392"
.ATT_COM R49 "Value" "120R"
.ATT_COM R49 "Cost25" "0.023"
.ADD_COM R5 "0805"
.ATT_COM R5 "Cost100" "0.006"
.ATT_COM R5 "Supplier" "RE"
.ATT_COM R5 "PCB Footprint" "0805"
.ATT_COM R5 "Cost1" "0.023"
.ATT_COM R5 "timestamp" "000D12E8"
.ATT_COM R5 "Cost1000" "0.00710"
.ATT_COM R5 "Pack" "100"
.ATT_COM R5 "Source Package" "R"
.ATT_COM R5 "Order Code" "72-4392"
.ATT_COM R5 "Value" "120R"
.ATT_COM R5 "Cost25" "0.023"
.ADD_COM R50 "0805"
.ATT_COM R50 "Cost100" "0.006"
.ATT_COM R50 "Supplier" "RE"
.ATT_COM R50 "Cost1" "0.023"
.ATT_COM R50 "PCB Footprint" "0805"
.ATT_COM R50 "timestamp" "000DAABD"
.ATT_COM R50 "Cost1000" "0.00710"
.ATT_COM R50 "Pack" "100"
.ATT_COM R50 "Source Package" "R"
.ATT_COM R50 "Order Code" "72-4392"
.ATT_COM R50 "Value" "120R"
.ATT_COM R50 "Cost25" "0.023"
.ADD_COM R6 "0805"
.ATT_COM R6 "Cost100" "0.006"
.ATT_COM R6 "Supplier" "RE"
.ATT_COM R6 "PCB Footprint" "0805"
.ATT_COM R6 "Cost1" "0.023"
.ATT_COM R6 "timestamp" "000D29A6"
.ATT_COM R6 "Cost1000" "0.00710"
.ATT_COM R6 "Pack" "100"
.ATT_COM R6 "Source Package" "R"
.ATT_COM R6 "Order Code" "72-4392"
.ATT_COM R6 "Value" "120R"
.ATT_COM R6 "Cost25" "0.023"
.ADD_COM R7 "0805"
.ATT_COM R7 "Cost100" "0.006"
.ATT_COM R7 "Supplier" "RE"
.ATT_COM R7 "PCB Footprint" "0805"
.ATT_COM R7 "Cost1" "0.023"
.ATT_COM R7 "timestamp" "000D29D3"
.ATT_COM R7 "Cost1000" "0.00710"
.ATT_COM R7 "Pack" "100"
.ATT_COM R7 "Source Package" "R"
.ATT_COM R7 "Order Code" "72-4392"
.ATT_COM R7 "Value" "120R"
.ATT_COM R7 "Cost25" "0.023"
.ADD_COM R8 "0805"
.ATT_COM R8 "Cost100" "0.006"
.ATT_COM R8 "Supplier" "RE"
.ATT_COM R8 "PCB Footprint" "0805"
.ATT_COM R8 "Cost1" "0.023"
.ATT_COM R8 "timestamp" "000D29EE"
.ATT_COM R8 "Cost1000" "0.00710"
.ATT_COM R8 "Pack" "100"
.ATT_COM R8 "Source Package" "R"
.ATT_COM R8 "Order Code" "72-4392"
.ATT_COM R8 "Value" "120R"
.ATT_COM R8 "Cost25" "0.023"
.ADD_COM R9 "0805"
.ATT_COM R9 "Cost100" "0.006"
.ATT_COM R9 "Supplier" "RE"
.ATT_COM R9 "PCB Footprint" "0805"
.ATT_COM R9 "Cost1" "0.023"
.ATT_COM R9 "timestamp" "000CC31C"
.ATT_COM R9 "Cost1000" "0.00710"
.ATT_COM R9 "Pack" "100"
.ATT_COM R9 "Source Package" "R"
.ATT_COM R9 "Order Code" "72-4392"
.ATT_COM R9 "Value" "120R"
.ATT_COM R9 "Cost25" "0.023"
.ADD_COM SW1 "see data"
.ATT_COM SW1 "Cost100" "0.135"
.ATT_COM SW1 "Supplier" "RE"
.ATT_COM SW1 "Cost1" "0.18"
.ATT_COM SW1 "PCB Footprint" "see data"
.ATT_COM SW1 "timestamp" "000D3EFB"
.ATT_COM SW1 "Source Package" "SW_T_SPDT"
.ATT_COM SW1 "Order Code" "76-0265"
.ATT_COM SW1 "Value" "SW_T_SPDT"
.ATT_COM SW1 "Man Ref" "SS-5806-012 series vertical"
.ADD_COM SW2 "SMT"
.ATT_COM SW2 "Cost100" "0.22"
.ATT_COM SW2 "Supplier" "RE"
.ATT_COM SW2 "PCB Footprint" "SMT"
.ATT_COM SW2 "Cost1" "0.28"
.ATT_COM SW2 "timestamp" "000C8C6F"
.ATT_COM SW2 "Source Package" "SW_TC_SPST"
.ATT_COM SW2 "Manu" "Diptronics"
.ATT_COM SW2 "Order Code" "72-4190"
.ATT_COM SW2 "Man ref" "DTSMW-66N"
.ATT_COM SW2 "Value" "Button"
.ADD_COM SW3 "SMT"
.ATT_COM SW3 "Cost100" "0.22"
.ATT_COM SW3 "Supplier" "RE"
.ATT_COM SW3 "PCB Footprint" "SMT"
.ATT_COM SW3 "Cost1" "0.28"
.ATT_COM SW3 "timestamp" "000C7E1B"
.ATT_COM SW3 "Source Package" "SW_TC_SPST"
.ATT_COM SW3 "Manu" "Diptronics"
.ATT_COM SW3 "Order Code" "72-4190"
.ATT_COM SW3 "Man ref" "DTSMW-66N"
.ATT_COM SW3 "Value" "Button"

.ADD_TER IC3 42 "ALT0"
.TER JP1 2

.ADD_TER IC3 38 "ALT2"
.TER JP1 6

.ADD_TER IC3 35 "ALT3"
.TER JP1 8

.ADD_TER IC2 G6 "XIL1"
.TER JP1 3

.ADD_TER IC2 E5 "XIL3"
.TER JP1 7

.ADD_TER IC2 E7 "XIL2"
.TER JP1 5

.ADD_TER IC2 F5 "XIL0"
.TER JP1 1

.ADD_TER JP2 1 "N864718"
.TER IC5 9

.ADD_TER JP2 3 "N864801"
.TER IC5 10

.ADD_TER JP2 5 "N864884"
.TER IC5 11

.ADD_TER JP2 7 "N864967"
.TER IC5 13

.ADD_TER IC2 D7 "NET0"
.TER IC3 34

.ADD_TER IC2 D6 "NET1"
.TER IC3 33

.ADD_TER IC3 39 "NALT1"
.TER IC1 2

.ADD_TER R1 2 "N851510"
.TER IC1 3
C1 1

.ADD_TER IC1 4 "N851502"
.TER R1 1
IC1 5

.ADD_TER IC1 6 "CLOCKS"
.TER IC3 37
IC2 B7

.ADD_TER IC1 10 "CLOCKF"
.TER IC3 40
IC2 B6

.ADD_TER IC1 9 "N851026"
.TER R2 2
C2 1

.ADD_TER IC1 8 "N850953"
.TER R2 1
IC1 11

.ADD_TER IC5 21 "NWE"
.TER IC3 28
R48 1

.ADD_TER IC5 20 "NOE"
.TER IC3 31
R47 1

.ADD_TER IC1 7 "GND"
.TER CN1 4
IC2 F3
JP7 3
JP7 2
IC3 4
C6 2
C7 2
C2 2
IC1 13
CN2 2
CN1 3
CN1 11
IC5 12
CN1 12
C1 2
IC2 A5
JP4 8
JP4 7
JP4 5
JP4 4
JP4 3
JP4 2
CN1 10
IC5 18
SW2 2
JP7 5
JP7 4
CN1 6
CN1 8
IC3 16
C11 2
IC3 30
JP7 8
JP7 7
IC4 4
R39 1
R38 1
R42 1
R41 1
R37 1
R36 1
R32 1
R31 1
R29 1
R45 1
R44 1
CN1 19
R46 1
C5 2
JP4 1
JP7 9
C9 2
JP7 10
IC3 24
R33 1
IC4 7
IC3 11
CN1 14
CN1 16
R34 1
IC4 3
CN1 20
D1 1
R43 1
C3 2
D9 1
D3 1
C8 2
R40 1
JP4 6
D4 1
JP7 6
C10 2
IC4 1
R50 2
CN1 18
R35 1
C4 2
JP4 10
IC3 36
D6 1
D8 1
JP4 9
D7 1
SW3 2
SW1 3
D2 1
R30 1
IC2 D1
IC4 2
D5 1
JP7 1

.ADD_TER IC1 14 "3.3V"
.TER R13 2
CN1 1
IC2 C1
IC2 G3
IC2 F7
R12 2
R3 2
R4 2
IC4 8
JP5 1
JP5 5
JP5 3
JP5 7
JP5 9
JP5 11
JP5 13
JP5 15
JP5 19
JP5 17
JP6 20
JP6 18
JP6 14
JP6 12
JP6 2
JP6 4
JP6 6
JP6 8
JP6 10
JP6 16
IC3 29
IC3 9
IC3 17
IC3 41
C5 1
C4 1
C11 1
C10 1
C7 1
C6 1
C9 1
C8 1
C3 1
IC5 24
SW1 1
CN2 1
R48 2
R47 2

.ADD_TER R3 1 "SDA"
.TER IC4 5
IC3 43
IC2 G7

.ADD_TER R4 1 "SCL"
.TER IC4 6
IC3 44
IC2 A7

.ADD_TER JP6 11 "DIL14"
.TER CN3 15
IC5 2
IC3 22
R43 2

.ADD_TER CN3 4 "DIL3"
.TER JP5 8
JP2 8
IC3 6
R32 2

.ADD_TER CN3 1 "DIL0"
.TER JP5 2
JP2 2
IC3 2
R29 2

.ADD_TER CN3 10 "DIL9"
.TER JP5 20
IC5 7
IC3 15
R38 2

.ADD_TER JP6 15 "DIL12"
.TER CN3 13
IC5 4
IC3 20
R41 2

.ADD_TER CN3 5 "DIL4"
.TER JP5 10
IC5 14
IC3 8
R33 2

.ADD_TER JP6 19 "DIL10"
.TER CN3 11
IC5 6
IC3 18
R39 2

.ADD_TER JP6 17 "DIL11"
.TER CN3 12
IC5 5
IC3 19
R40 2

.ADD_TER JP6 3 "DIL18"
.TER CN3 19
IC2 F6
R7 2

.ADD_TER CN3 2 "DIL1"
.TER JP5 4
JP2 4
IC3 3
R30 2

.ADD_TER JP6 1 "DIL19"
.TER CN3 20
IC2 E6
R8 2

.ADD_TER JP6 13 "DIL13"
.TER CN3 14
IC5 3
IC3 21
R42 2

.ADD_TER CN3 6 "DIL5"
.TER JP5 12
IC5 15
IC3 10
R34 2

.ADD_TER JP6 5 "DIL17"
.TER CN3 18
IC3 27
R6 2
R46 2

.ADD_TER CN3 3 "DIL2"
.TER JP5 6
JP2 6
IC3 5
R31 2

.ADD_TER CN3 8 "DIL7"
.TER JP5 16
IC5 17
IC3 13
R36 2

.ADD_TER IC3 32 "N895353"
.TER R49 1

.ADD_TER JP6 7 "DIL16"
.TER CN3 17
IC3 25
R5 2
R45 2

.ADD_TER CN3 9 "DIL8"
.TER JP5 18
IC5 8
IC3 14
R37 2

.ADD_TER D5 2 "N835810"
.TER R21 1

.ADD_TER R10 2 "LED6"
.TER IC2 B2

.ADD_TER CN3 7 "DIL6"
.TER JP5 14
IC5 16
IC3 12
R35 2

.ADD_TER R27 2 "LED11"
.TER IC2 E1

.ADD_TER JP6 9 "DIL15"
.TER CN3 16
IC3 23
R44 2

.ADD_TER R22 2 "LED15"
.TER IC2 F2

.ADD_TER R9 2 "LED0"
.TER IC2 A6

.ADD_TER D5 3 "N836102"
.TER R18 1

.ADD_TER CN1 5 "TDI"
.TER IC2 B3

.ADD_TER D8 2 "N835914"
.TER R27 1

.ADD_TER R21 2 "LED9"
.TER IC2 C3

.ADD_TER IC2 G2 "TDO/TDI"
.TER IC3 1

.ADD_TER CN1 7 "TMS"
.TER IC2 A2
IC3 7

.ADD_TER D3 3 "N835564"
.TER R11 1

.ADD_TER CN1 13 "TDO"
.TER R49 2

.ADD_TER D1 3 "N836208"
.TER R9 1

.ADD_TER CN1 9 "TCLK"
.TER IC3 26
IC2 A1
R50 1

.ADD_TER D7 2 "N836236"
.TER R26 1

.ADD_TER R16 2 "LED13"
.TER IC2 F1

.ADD_TER R18 2 "LED8"
.TER IC2 C2

.ADD_TER D9 2 "N835592"
.TER R28 1

.ADD_TER R14 2 "LED1"
.TER IC2 C5

.ADD_TER D2 2 "N835970"
.TER R15 1

.ADD_TER D3 2 "N835648"
.TER R16 1

.ADD_TER D6 2 "N835488"
.TER R22 1

.ADD_TER R19 2 "LED14"
.TER IC2 G1

.ADD_TER R23 2 "LED4"
.TER IC2 B4

.ADD_TER R26 2 "LED5"
.TER IC2 A3

.ADD_TER R15 2 "LED7"
.TER IC2 B1

.ADD_TER R25 2 "LED16"
.TER IC2 E3

.ADD_TER R28 2 "LED17"
.TER IC2 G4

.ADD_TER D1 2 "N836292"
.TER R14 1

.ADD_TER R17 2 "LED2"
.TER IC2 B5

.ADD_TER D6 3 "N835780"
.TER R19 1

.ADD_TER D4 3 "N836424"
.TER R17 1

.ADD_TER D7 3 "N836388"
.TER R23 1

.ADD_TER R20 2 "LED3"
.TER IC2 A4

.ADD_TER R24 2 "LED10"
.TER IC2 D2

.ADD_TER D8 3 "N836066"
.TER R24 1

.ADD_TER D2 3 "N835886"
.TER R10 1

.ADD_TER D9 3 "N835744"
.TER R25 1

.ADD_TER D4 2 "N836132"
.TER R20 1

.ADD_TER R11 2 "LED12"
.TER IC2 E2

.ADD_TER R13 1 "BUT1"
.TER SW3 3
IC2 G5

.ADD_TER R12 1 "BUT0"
.TER SW2 3
IC2 F4

.ADD_TER JP3 3 "N848809"
.TER R6 1

.ADD_TER JP3 1 "N848870"
.TER R5 1

.ADD_TER JP3 5 "N848931"
.TER R7 1

.ADD_TER JP3 7 "N848992"
.TER R8 1

.ADD_TER CN1 15 "GP0"
.TER IC2 C7

.ADD_TER IC2 C6 "GP1"
.TER SW1 2
CN1 17

.ADD_TER IC5 1 "N863487"
.TER JP3 2

.ADD_TER IC5 23 "N863570"
.TER JP3 4

.ADD_TER IC5 22 "N863653"
.TER JP3 6

.ADD_TER IC5 19 "N863736"
.TER JP3 8

.ADD_TER JP1 4 "ALT1"
.TER IC1 1

.END

XJTAG

2009-06-05T13:26:16Z

St12361:

This concerns users running latest version of XJTAG SW with the XJ-Tag Demo Board v 1.2.

Latest version of XJ-TAG SW is avaliable on request at: [http://www.XJTAG.com XJTAG.com]

The example files and tutorial that accompanies new versions of the XJ-TAG SW is not fully compatible with the XJ-TAG Demo board labeled v 1.2 that is avaliable at IFT.

First of all the Netlist must be exchanged with the original. Download netlist for v1.2 of the Demo Board here: * [[Demo.Net]] XJTAG Demo Board Tutorial Files and Instructions

XJTAG

2009-06-05T13:21:33Z

St12361:

XJTAG

2009-06-05T13:13:49Z

St12361: Created page with 'This concerns users running latest version of XJTAG SW with the XJ-Tag Demo Board v 1.2. Latest version of XJ-TAG SW is avaliable on request at: [http://www.XJTAG.com XJTAG.com]...'

This concerns users running latest version of XJTAG SW with the XJ-Tag Demo Board v 1.2.

Latest version of XJ-TAG SW is avaliable on request at: [http://www.XJTAG.com XJTAG.com]

The example files and tutorial that accompanies new versions of the XJ-TAG SW is not fully compatible with the XJ-TAG Demo board labeled v 1.2 that is avaliable at IFT.

All original files for the XJTAG Demo Board v 1.2 is zipped in this file: [[File:XJTAG-DB-1_2.zip]]

Microelectronics group

2009-06-05T13:04:07Z

St12361:

== Mikroelektronikk ==

Dokumentasjon for Mentor Graphics IC-programvaren finnes i katalogen /prog/mentor/mgc/ic.2006.2b/2006.2b_rhelx86linux/icflow_home/shared/pdfdocs eller ../htmldocs/

* [[IC studio]] Veiledning til IC-design ved hjelp av IC studio

* [[IC Station]] Tegne utlegg for integrerte kretser

* [[Expedition PCB]] Komme i gang med kretskortutlegg ved hjelp av Expedition PCB

* [[Modelsim/Questa]] Skrive og simulere VHDL-kode med Mentor Graphics ModelSim

* [[PCI-eksperiment]] Øving med HLT-RORC-prototypekort

* [[Cadence Virtuoso]]

* [[Xilinx]] Øving i bruk av Xilinx Project Studio

* [[FLTK GUI]] Graphical User Interface using FLTK

* [[Tutorials]] Tutorials from the web

* [[ADS]] Getting started with Agilent Advanced Design System

* [[XJTAG]] XJTAG Demo Board Tutorial Files and Instructions

* [[PHYS321]] Øvingsoppgaver i PHYS321

[[Category:Mikroelektronikk]]

Photomultipliers

2009-04-14T08:01:35Z

St12361:

==Critical Parameters==

{| border="1" cellpadding="5" cellspacing="0"
!Parameter
!Description
!Typical Value (Fast PTM)
!H6780-02
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|0,78 ns (0,2 s settling time)
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
 

[[Image:PMT_Parameters.jpg]]

==Overview of different PMT's==
{| border="1" cellpadding="2" cellspacing="0"
!Part ID
!Type
!Driving Voltage
!Gain
!Spectral Range (nm)
!Spectral Peak (nm)
!Dark Current (after 30 min)
!Rise Time (ns)
!Transit Time (TT)(ns)
!Transit Time Spread (TTS) (ns)
!Pricing
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r1166.php R1161]
|PMT - Head On
|1000 V
|1,0E+06
|300 to 650
|420
|1-6 nA
|2,5
|27
|2,8
|x
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5509-42.php R5505]
|PMT - Head On
|1750 V
|1,0E+06
|300 to 1400
|900
|10 nA
|3
|23
|1,5
|16 010 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3478.php R3478]
|PMT - Head On
|1700 V
|1,7E+06
|300 to 650
|420
|6 nA
|1,3
|14
|0,36
|3 837 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u-02.php 7400U-02]
|PMT - Head On
|800 V
|5,0E+05
|300 to 850
|500
|2 nA
|0,78
|5,4
|0,23
|6 404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r2083.php R2083]
|PMT - Head On
|3000 V
|2,5E+06
|300 to 650
|420
|100 nA
|0,7
|16
|0,37
|14 955 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u.php 7400-02]
|PMT - Head On
|800 V
|7,0E+05
|300 to 850
|420
|0,2 nA
|0,75
|5,4
|0,28
|6404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3809u-52.php R3809-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|2000/s
|0,15
|0,55
|0,025
|126 346 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5916u-52.php R5916U-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|0,5
|0,18
|1
|0,09
|148 643 SEK
|}
===So whats's up with the MCP's?===
Microchannel Plate PMT, has plates containing numerous small holes, microchannels, which are lined with a secondary emissive dynode material. Electrons are amplified as they drop down the voltage gradients across the microchannel plate.

MCP-PMT shows the fastes time response due to the restricted range of electron paths and short electron travel distance.

Disadvantage is lower gain and photocurrent typ at 100 nA vs. 10-100uA for dyanode PMT
 
[[Image:MCP-PMT.jpg]]

Lab Equipment

2009-04-14T07:55:57Z

St12361:

= Power Supplies =
== High Voltage ==
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How To's
|-
|CAEN 40 Channel High Voltage System
|High Voltage DC power supply equipped with 4x POS 200V, 4x NEG 200V, 4x POS 2000V and 2 x POS 15 kV outputs
|[[CAEN 40CH HV PSU]]
|-

|}

== 'Medium' Voltage ==
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!I/O
|-
|Elektro Automatik EA-PSI 6150-01
|150 V, 1,2A linear DC power supply
|RS232

|}

== Low Voltage ==
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!I/O
!Notes
|-

|TTi EL155
|15V, 5A linear DC power supply
|
|
|-

|TTi EL302D
|30V, 2A dual linear DC power supply
|
|
|-

|TTi QL355TP
|15V, 5A / 35V, 3A / 35V, 0,5A + Aux, dual DC power supply
|GPIB, RS232, USB
|
|-

|TTi QPX1200
|60V, 50A linear DC power supply
|USB, RS232, LAN
|
|-

|Oltronix Labpac 800T
|15V/35V, 2A/1,1A
|
|
|-

|ITT AX 322
|2x 30V, 2,5A
|
|Noisy
|-

|}

= Standalone measuring =
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How to's
!I/O
|-

|Tektronix MSO4034
|Mixed Signal Oscilloscop, 350 Mhz, 2,5Gs/s
|
|LAN, USB
|-

|Agilent MSO7054A
|Mixed Signal Oscilloscop, 500 Mhz, 4Gs/s
|
|LAN, USB
|-

|Keithley 2700
|Multimeter / Data Acquisition System, 20 Channel
|
|GPIB, RS232
|-

|Keithley 2100
|6 1/2 Digit Multimeter
|
|USB

|}

= Pulse Generators =
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How To's
!I/O
|-

|Agilent 33250A
|80 Mhz Arbitrary Function Waveform Generator
|
|GPIB, RS232
|-

|Philips PM 5715
|Pulse / Waveform Generator 50 Mhz
|
|
|-

|}

= Amplifiers =
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How To's
|-
|Phillips Scientific 6954
|Wideband Amplifier, Gain: 100, Input Voltage: 10-28V.
|[[http://www.phillipsscientific.com/pdf/6954ds.pdf Info]]
|-
|Ortec VT120
|Amplifier, Gain: 200, Input Voltage: 12V.
|[[http://www.ortec-online.com/pdf/vt120.pdf Info]]

|}

= VME devices =

{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How To's
|-
|Caen V2818
|PCI bridge to VME controller
|

|-
|Caen V2718
|VME controller
|

|-
|Caen V1729a
|14 bit, 4 channel ADC
|

|-
|Caen V965a
|QDC
|

|-
|National Instruments VME-MXI-2
|VME controller
|

|-
|Atlas TPLL
|Turbo Pixel Low Level card (TPLL)
|[[http://physik2.uni-goettingen.de/~jgrosse/TurboDAQ/#PLLPCC TPLL&TPCC Info]]

|}
= Photomultipliers =
{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How To's
|-
|2 x Hamamatsu H6780-02, S.NO: 0003 & 0004
|Photomultiplier Module, Input Voltage: 15V, Gain: 1:10E4, Gain Control Voltage: 0,25-0,9 V. Max output current: 100uA!
|[[Photomultipliers]]
|}

PET Project

2009-04-14T07:51:39Z

St12361:

== Goal ==
The MEDUSA project focuses on R&D for high energy physics instrumentation with two important and dependant goals. One is to contribute to the research for future particle detectors and develop new improved detectors for the LHC upgrade as well as the planned international linear collider. The other is to provide new technologies for medical imaging devices such as PET. With this, we hope to contribute to bridging the gap between the particle physics research and the medical technology to fully take advantage of the latest development.

[[Image:PETEscan.jpg|frameless|none|500px]]

Two complementary detector technologies are highly interesting for medical applications. First, the compact calorimeter is a new technology for detection of photons and hadrons, based on a new type of silicon photomultipliers. These detectors form the base of modern medical imaging technology where precise localisation of radioactive tracers in the body. Aquisition speed and sensitivity are two central challenges for high energy physics. In addition, these detectors can be used to develop Time-of-Flight measurements.

The 3D semiconductor devices are based on another new technology, aiming to provide particle and radiation detection by the use of 3 dimensional silicon pixels. The advantage of this method is that these sensors have improved radiation hardness as well as a better to-the-edge detection. A substancial challenge is to provide thin devices and 3D integration, one of the requirement for linear accelerators. Semiconductor detectors are widely used in imaging spectroscopy and particle tracking of ionising radiation, both for charged particles and photons.

This project is set up with the collaboration of the new PET center at Haukeland University Hospital and we will closely collaborate with their researchers. Other research partners are the University of Oslo as well as the CLIC, ALICE and the ATLAS collaboration at CERN and the ILC project.

== General PET technology ==
Positron Emission Tomography (PET) is recognized as a great medical imaging devices thanks to its non invasive technology. PET is a type of nuclear medicine procedure that measures metabolic activity of the cells of body tissues. PET is actually a combination of nuclear medicine and biochemical analysis. Used mostly in patients with brain or heart conditions and cancer, its big advantage is to identify the onset of a disease process before
anatomical changes (that can be seen with other imaging processes such as computed tomography (CT) or MRI) related to the disease.

=== Radiotracers ===
[[Image:MAPD_radiotracer.JPG‎|frame|right|200px|Fluorodeoxyglucose-FDG]]
[[Image:MAPD_positronelectronannihilation.JPG‎‎|frame|left|200px|Positron - Electron Annihilation]]
The PET technology is based on radioactive emission. Radioactive substances are combined to molecules that the studied cells use particularly in their metabolism. These tracers are radioactive substances. The first step in PET imaging is the production of radionuclides by a cyclotron. These
radionuclides will be attached to molecules used by the body before being injected to the patient by intravenous way. The molecule and the adionuclide form the radiotracer. The tracer is injected to the patient and, following the half life of the radionuclide, it will become stable by
emitting a positron and a neutrino (the proton which stays in excess will become a neutron). Then, the emitted positron travels a short distance before
encountering an electron. When they meet each other, the two particles combine and annihilate each other resulting in the emission of two 511 keV gamma rays in opposite directions.

=== Scintillators ===
[[Image:MAPD_crystaltransition.JPG‎ |frame|left|200px|Electronic transition in a crystal]]
A scintillator is a substance that absorbs high energy and then, in response, emits photons. Scintillators are defined by their light output (number of emitted photons per unit absorbed energy), short fluorescence decay times, and optical transparency at wavelengths of their own specific emission energy. The high Z-value of the constituents and high density of inorganic crystals favour their choice for gamma-rays spectroscopy (rather than organic crystal) because heavy nucleuses accept better gammas than light nucleus. The scintillation mechanism in inorganic materials depends on energy states determined by the crystal lattice of the material. Absorption of energy can result in the elevation of an electron from its normal position in the valence band across the gap in the conduction ban, leaving a hole in the valence band. A charged particle passing through the detection medium will form a large number of electron-hole pairs, created by the elevation of electrons from the valence to the conduction band. The positive hole will quickly drift to the location of an impurity and ionize it, because the ionization energy of this impurity will be less than that of a typical lattice site. Meanwhile, the electron is free to migrate through the crystal and will do so until it encounters an ionized activator. At this point, the electron can drop into the impurity site, creating a neutral impurity configuration which can have its own set of excited energy states. If the activator state that is formed is an excited configuration with an allowed transition to the ground state, its deexcitation will occur very quickly and with high probability for the emission of the corresponding photon. The migration time for the electronics is shorter than the drop-out time: therefore, the decay time of these states determines the time characteristics of the emitted scintillation light. In order to fully utilize the scintillation light, the spectrum should fall near the wavelength region of maximum sensitivity for the device used to detect the light.

{| border="1" cellpadding="2" cellspacing="0"
!
!NaI(Ti)
!BGO
!LSO
!LYSO
|-
|'''ZE'''
|50
|74,2
|65
|65
|-
|'''Density'''
|3,67
|7,13
|7,35
|7,1
|-
|'''Attenuation coeff (cm-1)'''
|0,34
|0,95
|0,8
|0,83
|-
|'''Decay time (ns)'''
|230
|300
|40
|42
|}

We see, through this chart, that the discovery of the LSO and LYSO crystals have helped to make some progresses. LSO and LYSO crystal are the best compromise for a high attenuation coefficient and a short decay time, two useful properties to improve time resolution in PET scanner.

=== Coincidence detection ===
[[Image:MAPD_coincidenceprinciple.JPG‎ |frame|none|200px|Coincidence detection principle]]
In a PET camera, each detector generates a time pulse when it registers an incident photon. These pulses are then combined in coincidence circuitry, and if the pulses fall within a short time-window, they are deemed to be coincident. A diagram of this process is shown below:
A coincidence event is assigned to a line of response (LOR) joining the two relevant detectors. Coincidence events in PET fall into 3 categories: true, scattered and random.

[[Image:MAPD_coincidencecategories.JPG|frame||200px|3 different coincidence detection events]]

* '''True coincidences''' occur when both photons from an annihilation event are detected by detectors in coincidence, neither photon undergoes any form of interaction prior to detection, and no other event is detected within the coincidence time-window.

* A '''scattered coincidence''' is one in which one of the detected photons (sometimes both) has undergone at least one Compton scattering event prior to detection. Since the direction of the photon is changed during the Compton scattering process, it is highly likely that the resulting coincidence event will be assigned to the wrong LOR. Scattered coincidences add a background to the true coincidence distribution which changes slowly with position, decreasing contrast and causing the isotope concentrations to be overestimated. They also add statistical noise to the signal. The number of scattered events detected depends on the volume and attenuation characteristics of the object being imaged.

* '''Random coincidences''' occur when two photons, not arising from the same annihilation event, are incident on the detectors within the coincidence time window of the system. As with scattered events, the number of random coincidences detected also depends on the volume and attenuation characteristics of the object being imaged, and on the geometry of the camera. The distribution of random coincidences is fairly uniform across the field of view and will cause isotope concentrations to be overestimated if not corrected for. Random coincidences also add statistical noise to the data.

=== Time of Flight ===
Time-of-flight PET takes advantage of the difference in arrival times of two photons from the same annihilation event to infer spatial information of this event. A detected coincidence between two crystals will have a time difference for any annihilation event that does not occur at the midpoint between the detectors, this time difference is used to place the position of the event.
[[Image:MAPD tofprinciple.jpg‎ |frame|none|200px|Time of flight principle]]
[[Image:MAPD tofprinciple2.JPG|frame|none|200px|Time of flight principle]]

== Technology ==
=== Avalanche Photodiodes ===
[[Image:MAPD structure.jpg‎|frame|right|200px|Structure of MAPD]]
An APD is basically a p-n junction diode operated at large reverse bias voltage. The physical mechanism which avalanche gain depends, is the impact ionization. It occurs when the electric field in the depletion region is strong enough: an electron colliding with a bound valence electron transfers enough energy to this electron to ionize it. The additional carriers can gain sufficient energy from the electric field to cause further impact ionization, creating an avalanche of carriers.

* '''proportional mode'''
In a proportional counter, each original electron leads to an avalanche which is basically independent of all other avalanches formed from the other electrons associated with the original ionizing event. The collected charge remains proportional to the number of original electrons.
[[Image:MAPD proportionalmode.jpg‎ ‎|frame|right|200px|proportional mode]]

* '''Geiger mode'''
With a higher electric field, a situation is created, in which one avalanche trigger itself a second avalanche at a different position.
[[Image:MAPD geigermode.jpg‎‎|frame|right|200px|Geiger mode]]
[[Image:MAPD_passivequenching.jpg‎‎|frame|right|200px|passive quenching]]

The difference between both modes relies on the holes: in Geiger mode, they trigger avalanches, whereas in proportional mode they have not enough energy to do so. From the critical value of the electric field (corresponding to the breakdown voltage), a self propagating chain reaction occurs. In principle, an exponentially growing number of avalanches could be created.

* '''b- Passive quenching'''
The avalanche photodiode (i. e. pixel for the silicon photomultiplier) is connected to the power supply through a large series resistor Rs. If the current through the diode tends to zero, the voltage across the diode equals Vbias, which will be larger than the breakdown voltage. So, when the diode breaks down, the series resistor reduces the voltage across the APD, what quenches the avalanche. After the breakdown is quenched, the diode is recharged through the resistor. The APD is now ready to receive another photon.

=== different MAPDs ===
The MAPDs are 3 mm *3 mm, composed of 104 pixels /mm2 (9.104 pixels in total). They should be operated in inverse direction: anode should be grounded, while positive voltage in range 132-136V (it depends on the MAPDs and it is reported by the manufacturer). Exceeding the voltage 137V leads to unstable operation and even to the destruction of MAPD.

The resistance of each pixel allows the passive quenching. Pixels are electrically decoupled from each other by polysilicon resistors and are connected by common Al strips, in order to readout the MAPD signal.
Each MAPD pixel operates as a binary device but MAPD in whole is an analogue detector. The output signal allows us to determine the number of fired pixels: in fact, the output signal is proportional to the number of fired pixels. The MAPD is intrinsically very fast due to the very small width of the depletion region and the extremely short Geiger type discharge.
We must keep in mind that the name of the device depends on the manufacturer. MPPC (for Multi-Pixel Photon Counter) and SiPM (Silicon PhotoMultiplier) are two other usual names.

=== Properties of the devices ===
* '''Time resolution''': even if photons simultaneously enter different pixels at the same time, the output pulse from each pixel will not necessarily be the same time so that a fluctuation or time jitter occurs. When two photons enter APD pixels at a certain time difference which is shorter than this jitter, then that time difference is impossible to detect. Time resolution is the minimum time difference that can be detected by APD pixels and is defined as FWHM of the distribution of the time jitter.

* '''Photon Detection Efficiency (PDE)''': this is a measure of what percent of the incident photons were detected.

* '''Dark count''': output pulses are produced not only by photon-generated carriers but also by thermally-generated dark current carriers. The dark current pulses are measured as dark count which then causes detection errors. Although increasing the reverse voltage improves photon detection efficiency, it also increases the dark count. The dark count can be reduced by lowering the temperature.

* '''Absolute gain''': the absolute gain is the number of charges which have been created at the output of the MAPD when one photon has hit this device.

* '''Quantum efficiency (QE)''': quantum efficiency is a value showing the number of electrons or holes created as photocurrent divided by the number of incident photons, and is usually expressed as a percent.

* '''Afterpulse''': afterpulses are spurious pulses following the true signal, which occur when the generated carriers are trapped by crystals defects and then release at a certain delay time. A fterpulses cause detection errors. The lower the temperature, the higher the probability that carriers may be trapped by crystal defects, so afterpulses will increase.

* '''Crosstalk''': in an avalanche multiplication process, photons might be generated which are different from photons initially incident on an APD pixel. If those generated photons are detected by other APD pixels, then the MAPD output shows a value higher than the number of photons that were actually input and detected by the MAPD. This phenomenon is thought to be one of the causes of crosstalk in the MAPD.

== Characterisation Cell ==
== Characterisation setup and results ==

[[User:Dfe002|Dominik]] 09:04, 12 March 2009 (CET)

[[Category:Detector lab]]

Lab Equipment

2009-04-14T07:46:42Z

St12361:

Synthese av VHDL

2009-03-15T20:23:21Z

St12361: Corrected to run properly under QuestaSim v.6.4a

===Synthesisering av vhdl kode===

Grunnen til at vi skal synthesisere koden, er at vi må lage beskrivelse av koden tilpassa ein krets.

Vi vil no prøve å synthesisere vhdl kode. Og etterpå vil vi lage ein testbenk der vi samanliknar utsignale frå den sythisierte og den opprinnelige koden. Vi bruker ein alu som eksempel.

==Precision==

<pre>
mentor
precision
</pre>

Pass på at lisensen for Quartus er korrekt satt opp, og at Precision finner Quartus.
Sett opp lisensen i Quartus ved å starte Quartus, og velg menyen

Precision er eit program som bruker Quartus til å synthisiere vhdl kode. For å starte opp dette skriv: presision i eit terminalvindu. Vel deretter New Project, og deretter Add input file(i dette tilfelle alu_example.vhdl). Så går vi inn på Setup design, velger ein kretsprodusent, den ønska kretsen og designfrekvens(i vårt tilfelle valgte vi Altera APEX 20KE med frekvens 200MHz). Trykk så compile, og synthesize. No kan vi sjå på den generte kretsen i RTL Schematic og Technology Schematic(syntese med den valgte kretsen).

Hvis du får en "ROOTDIR"-error, mangler det en variabel. Skriv følgende i terminalen:

<pre>
setenv QUARTUS_ROOTDIR /prog/altera/quartus6.0

</pre>

==Modelsim==

Start opp Modelsim, lag nytt prosjekt og legg til vhdl fila(alu_example.vhdl). Så legg vi til fila som Precision generte i prosjektdir til 'precision/prosjektnavn_temp_1/simulation/modelsim/prosjektnavn.vho' (i vårt tilfelle 'alu/add_sub_alu_temp_1/simulation/modelsim/add_sub_alu.vho').

Legg til mapping av alterabiblioteket

vmap apex20ke /prog/altera/vhdl/apex20ke

Deretter legger vi til ei ny vhdl fil der vi skal lage testbenken vår. Vi legger til ein komponent av den opprinnelige og den synthesiserte vhdl koden. Vi koblar alle inngangane til samme signal på testbenken, og gir ut 2 forskjellige utsignal for å samanlikne ved hjelp av assert(sjå fila alu_tb.vhdl). Vi må ha ulike entitynavn på den synthesiserte og opprinnlige komponenten, ellers vil ikkje simuleringa virka. På grunn av at utsignala av dei to komponentane ikkje skifta heilt synkront, testa vi berre kvart nanosekund ved å putta assert inn i ein process med wait for 1ns:

<pre>
test : process
begin
wait for 1 ns;
assert (data_out = data_out_synt)
report "Data ut er ulik"
severity Error;
end process test;
</pre>

Når vi har laga testbenken, kompilerer vi(husk å kompilere i rett rekkefølge med compileorder->autogenerate) filene.

==Simulering med timing==

<pre>
vsim -t ps alu_tb -sdfmax :alu_tb:ali=/heim/yngve/vhdl/syntese/alu_temp_1/simulation/modelsim/add_sub_alu_vhd.sdo
</pre>

Vi kan sjå at i dei første 50 nanosekunda er utsignala ulike. Dette er fordi før første klokkeflanke er verdiane udefinert i den opprinnelige komponenten, medan den synthesisere ikkje kan ha udefinerte verdiar. I Modelsim vil vi derfor få ein del feilmeldingar dei første 50 nanosekunda.

==Konklusjon==

Vi kan teste om den synthesisere komponenten oppfører seg likt med den opprinnelige komponenten ved å koble begge to til samme testbenk. Vi fekk problem i overgangane når vi testa kontinuerlig, så vi løyste problemet ved å berre teste kvart naonosekund. Bortsett frå dei første 50 nanosekunda(sjå grunn over) kan vi sjå at begge komponetane gir ut samme utsignal. Vi prøvde å bruke samme enitynavn på begge komponentane med ulik arcitechture, men fekk berre lov å kompilere og ikkje simulere. Vi kan derfor konkludere med at desse må ha ulike navn.

==Kode==

===Kode til alu_example.vhdl===

<pre>
LIBRARY ieee;
USE ieee.std_logic_1164.All;
USE ieee.std_logic_unsigned.all;

ENTITY add_sub_alu IS
PORT (clk, rst : IN std_logic;
enable_in : IN std_logic;
start : IN std_logic;
enable : IN std_logic;
do_add : IN std_logic;
do_subtract : IN std_logic;
do_hold : IN std_logic;
data_in : IN std_logic_vector(3 DOWNTO 0);
data_out : OUT std_logic_vector (3 DOWNTO 0) BUS);
END add_sub_alu;

ARCHITECTURE algorithm OF add_sub_alu IS
TYPE states IS (hold, reset, add, subtract);
SIGNAL state_var : states;
SIGNAL reg, int_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL latched_data_in: std_logic_vector(3 DOWNTO 0);
BEGIN

latch: PROCESS (enable_in, data_in)is
BEGIN
IF (enable_in = '1') THEN
latched_data_in <= data_in;
END IF;
END PROCESS latch;

fsm: PROCESS (clk, rst) is
BEGIN
IF (rst = '0') THEN
state_var <= reset;
ELSIF (clk = '1' AND clk'LAST_VALUE = '0') THEN
CASE state_var IS
WHEN hold => IF (start = '1') THEN
state_var <= reset;
END IF;
WHEN reset => IF (do_add = '1') THEN
state_var <= add;
ELSIF (do_subtract = '1') THEN
state_var <= subtract;
END IF;
WHEN add => IF (do_hold = '1') THEN
state_var <= hold;
ELSIF (do_subtract = '1') THEN
state_var <= subtract;
END IF;
WHEN subtract => IF (do_hold = '1') THEN
state_var <= hold;
ELSIF (do_add = '1') THEN
state_var <= add;
END IF;
WHEN OTHERS => state_var <= reset;
END CASE;
END IF;
END PROCESS fsm;

alu: PROCESS (state_var, latched_data_in, reg)is
BEGIN
CASE state_var IS
WHEN add => int_reg <= reg + latched_data_in;
WHEN subtract => int_reg <= reg - latched_data_in;
WHEN reset => int_reg <= "0000";
WHEN hold => int_reg <= reg;
WHEN OTHERS => int_reg <= reg;
END CASE;
END PROCESS alu;

mem: PROCESS (clk) is
BEGIN
IF (clk = '1' AND clk'LAST_VALUE = '0') THEN
reg <= int_reg;
END IF;
END PROCESS mem;

tri: PROCESS (enable, reg) is
BEGIN
FOR i IN 3 DOWNTO 0 LOOP
IF (enable = '1') THEN
data_out(i) <= reg(i);
ELSE
data_out(i) <= null;
END IF;
END LOOP;
END PROCESS tri;

END algorithm;
</pre>

===Koden til add_sub_alu.vho===

<pre>
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version"

-- DATE "02/18/2005 13:34:52"

--
-- Device: Altera EP20K200EQC208-1 Package PQFP208
--

--
-- This VHDL file should be used for MODELSIM (VHDL OUTPUT FROM QUARTUS II) only
--

LIBRARY IEEE, apex20ke;
USE IEEE.std_logic_1164.all;
USE apex20ke.apex20ke_components.all;

ENTITY add_sub_alu_synt IS
PORT (
enable : IN std_logic;
clk : IN std_logic;
do_hold : IN std_logic;
rst : IN std_logic;
do_add : IN std_logic;
do_subtract : IN std_logic;
enable_in : IN std_logic;
data_in : IN std_logic_vector(3 DOWNTO 0);
start : IN std_logic;
data_out : OUT std_logic_vector(3 DOWNTO 0)
);
END add_sub_alu_synt;

ARCHITECTURE structure OF add_sub_alu_synt IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL ww_enable : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_do_hold : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_do_add : std_logic;
SIGNAL ww_do_subtract : std_logic;
SIGNAL ww_enable_in : std_logic;
SIGNAL ww_data_in : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_start : std_logic;
SIGNAL ww_data_out : std_logic_vector(3 DOWNTO 0);
SIGNAL if0a5x13_aCOMBOUT : std_logic;
SIGNAL start_acombout : std_logic;
SIGNAL data_in_a2_a_acombout : std_logic;
SIGNAL do_subtract_acombout : std_logic;
SIGNAL do_hold_acombout : std_logic;
SIGNAL n5831x3 : std_logic;
SIGNAL do_add_acombout : std_logic;
SIGNAL n5831x2 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL rst_acombout : std_logic;
SIGNAL n544cx3 : std_logic;
SIGNAL n544cx2 : std_logic;
SIGNAL state_var_1 : std_logic;
SIGNAL data_in_a0_a_acombout : std_logic;
SIGNAL enable_in_acombout : std_logic;
SIGNAL latched_data_in_0 : std_logic;
SIGNAL nfc54x2 : std_logic;
SIGNAL cin : std_logic;
SIGNAL a_2_dup_240 : std_logic;
SIGNAL nf0a5x2 : std_logic;
SIGNAL reg_0 : std_logic;
SIGNAL enable_acombout : std_logic;
SIGNAL data_in_a1_a_acombout : std_logic;
SIGNAL latched_data_in_1 : std_logic;
SIGNAL nf0a5x8 : std_logic;
SIGNAL nf0a5x10 : std_logic;
SIGNAL nf0a5x9 : std_logic;
SIGNAL a_2_dup_239 : std_logic;
SIGNAL reg_1 : std_logic;
SIGNAL latched_data_in_2 : std_logic;
SIGNAL nf0a5x6 : std_logic;
SIGNAL nf0a5x7 : std_logic;
SIGNAL a_2_dup_238 : std_logic;
SIGNAL reg_2 : std_logic;
SIGNAL data_in_a3_a_acombout : std_logic;
SIGNAL latched_data_in_3 : std_logic;
SIGNAL nf0a5x4 : std_logic;
SIGNAL nf0a5x5 : std_logic;
SIGNAL a_2 : std_logic;
SIGNAL reg_3 : std_logic;
SIGNAL ALT_INV_rst_acombout : std_logic;

BEGIN

ww_enable <= enable;
ww_clk <= clk;
ww_do_hold <= do_hold;
ww_rst <= rst;
ww_do_add <= do_add;
ww_do_subtract <= do_subtract;
ww_enable_in <= enable_in;
ww_data_in <= data_in;
ww_start <= start;
data_out <= ww_data_out;
ALT_INV_rst_acombout <= NOT rst_acombout;

start_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_start,
combout => start_acombout);

data_in_ibuf_2 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(2),
combout => data_in_a2_a_acombout);

do_subtract_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_subtract,
combout => do_subtract_acombout);

do_hold_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_hold,
combout => do_hold_acombout);

ib0e1x3 : apex20ke_lcell
-- Equation(s):
-- n5831x3 = do_hold_acombout & state_var_1

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datac => do_hold_acombout,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n5831x3);

do_add_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_add,
combout => do_add_acombout);

ib0e1x2 : apex20ke_lcell
-- Equation(s):
-- n5831x2 = n544cx3 & state_var_1 & !do_subtract_acombout # !state_var_1 & !start_acombout

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "3050",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => start_acombout,
datab => do_subtract_acombout,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n5831x2);

clk_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_clk,
combout => clk_acombout);

rst_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_rst,
combout => rst_acombout);

reg_state_var_0 : apex20ke_lcell
-- Equation(s):
-- n544cx3 = DFFE(n5831x3 # n5831x2 # !n544cx3 & do_add_acombout, GLOBAL(clk_acombout), GLOBAL(rst_acombout), , )

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FFDC",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
dataa => n544cx3,
datab => n5831x3,
datac => do_add_acombout,
datad => n5831x2,
clk => clk_acombout,
aclr => ALT_INV_rst_acombout,
devclrn => devclrn,
devpor => devpor,
regout => n544cx3);

ib0e2x3 : apex20ke_lcell
-- Equation(s):
-- n544cx2 = !n544cx3 & !state_var_1 & do_add_acombout # do_subtract_acombout

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "000E",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => do_add_acombout,
datab => do_subtract_acombout,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n544cx2);

reg_state_var_1 : apex20ke_lcell
-- Equation(s):
-- state_var_1 = DFFE(n544cx2 # !do_hold_acombout & state_var_1, GLOBAL(clk_acombout), GLOBAL(rst_acombout), , )

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FF50",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
dataa => do_hold_acombout,
datac => state_var_1,
datad => n544cx2,
clk => clk_acombout,
aclr => ALT_INV_rst_acombout,
devclrn => devclrn,
devpor => devpor,
regout => state_var_1);

data_in_ibuf_0 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(0),
combout => data_in_a0_a_acombout);

enable_in_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_enable_in,
combout => enable_in_acombout);

id8dfx3 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_0 = enable_in_acombout & data_in_a0_a_acombout # !enable_in_acombout & latched_data_in_0

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CACA",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => latched_data_in_0,
datab => data_in_a0_a_acombout,
datac => enable_in_acombout,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_0);

id8dfx2 : apex20ke_lcell
-- Equation(s):
-- nfc54x2 = latched_data_in_0 $ (!n544cx3 # !state_var_1)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C30F",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datac => latched_data_in_0,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nfc54x2);

id8dfx1 : apex20ke_lcell
-- Equation(s):
-- cin = state_var_1 & !n544cx3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "00CC",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => cin);

ifc54x2 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_240 = nfc54x2 $ reg_0 $ cin

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C33C",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => nfc54x2,
datac => reg_0,
datad => cin,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_240);

i197dx1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x2 = state_var_1 # !n544cx3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CCFF",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x2);

reg_reg_0 : apex20ke_lcell
-- Equation(s):
-- reg_0 = DFFE(a_2_dup_240 & state_var_1, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => a_2_dup_240,
datad => state_var_1,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_0);

enable_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_enable,
combout => enable_acombout);

data_in_ibuf_1 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(1),
combout => data_in_a1_a_acombout);

i2456x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_1 = enable_in_acombout & data_in_a1_a_acombout # !enable_in_acombout & latched_data_in_1

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CFC0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => data_in_a1_a_acombout,
datac => enable_in_acombout,
datad => latched_data_in_1,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_1);

i2456x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x8 = latched_data_in_1 $ (!state_var_1 # !n544cx3)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C333",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => latched_data_in_1,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x8);

if0a5x14 : apex20ke_lcell
-- Equation(s):
-- nf0a5x10 = reg_0 & nfc54x2 # cin # !reg_0 & nfc54x2 & cin

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FCC0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => reg_0,
datac => nfc54x2,
datad => cin,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x10);

if0a5x13 : apex20ke_lcell
-- Equation(s):
-- nf0a5x9 = CARRY(nf0a5x10)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
packed_mode => "false",
lut_mask => "00CC",
output_mode => "none")
-- pragma translate_on
PORT MAP (
datab => nf0a5x10,
devclrn => devclrn,
devpor => devpor,
cout => nf0a5x9);

if0a5x10 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_239 = reg_1 $ nf0a5x8 $ nf0a5x9
-- nf0a5x7 = CARRY(reg_1 & !nf0a5x8 & !nf0a5x9 # !reg_1 & !nf0a5x9 # !nf0a5x8)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "9617",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_1,
datab => nf0a5x8,
cin => nf0a5x9,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_239,
cout => nf0a5x7);

reg_reg_1 : apex20ke_lcell
-- Equation(s):
-- reg_1 = DFFE(state_var_1 & a_2_dup_239, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2_dup_239,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_1);

ia9f8x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_2 = enable_in_acombout & data_in_a2_a_acombout # !enable_in_acombout & latched_data_in_2

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "AFA0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => data_in_a2_a_acombout,
datac => enable_in_acombout,
datad => latched_data_in_2,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_2);

ia9f8x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x6 = latched_data_in_2 $ (!state_var_1 # !n544cx3)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C333",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => latched_data_in_2,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x6);

if0a5x7 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_238 = reg_2 $ nf0a5x6 $ !nf0a5x7
-- nf0a5x5 = CARRY(reg_2 & nf0a5x6 # !nf0a5x7 # !reg_2 & nf0a5x6 & !nf0a5x7)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "698E",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_2,
datab => nf0a5x6,
cin => nf0a5x7,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_238,
cout => nf0a5x5);

reg_reg_2 : apex20ke_lcell
-- Equation(s):
-- reg_2 = DFFE(state_var_1 & a_2_dup_238, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2_dup_238,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_2);

data_in_ibuf_3 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(3),
combout => data_in_a3_a_acombout);

ia9f5x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_3 = enable_in_acombout & data_in_a3_a_acombout # !enable_in_acombout & latched_data_in_3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F5A0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => enable_in_acombout,
datac => data_in_a3_a_acombout,
datad => latched_data_in_3,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_3);

ia9f5x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x4 = latched_data_in_3 $ (!n544cx3 # !state_var_1)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C30F",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datac => latched_data_in_3,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x4);

if0a5x4 : apex20ke_lcell
-- Equation(s):
-- a_2 = reg_3 $ (nf0a5x5 $ nf0a5x4)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
cin_used => "true",
packed_mode => "false",
lut_mask => "A55A",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_3,
datad => nf0a5x4,
cin => nf0a5x5,
devclrn => devclrn,
devpor => devpor,
combout => a_2);

reg_reg_3 : apex20ke_lcell
-- Equation(s):
-- reg_3 = DFFE(state_var_1 & a_2, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_3);

tri_data_out_0 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_0,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(0));

tri_data_out_1 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_1,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(1));

tri_data_out_2 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_2,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(2));

tri_data_out_3 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_3,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(3));
END structure;

</pre>

===Koden til alu_tb.vhdl===

<pre>
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;

entity alu_tb is
end entity alu_tb;

architecture struct of alu_tb is
--Deklaring av signal som skal koblast til komponentane.
--Alle innsignal er felles, medan vi har 2 forskjellige utsignal.
signal clk, reset : std_logic;
signal enable_in : std_logic;
signal start : std_logic;
signal enable : std_logic;
signal do_add : std_logic;
signal do_subtract : std_logic;
signal do_hold : std_logic;
signal data_in : std_logic_vector(3 downto 0);
signal data_out : std_logic_vector(3 downto 0);
signal data_out_synt : std_logic_vector(3 downto 0);

begin

--Deklarer komponenten alu.
alu : entity add_sub_alu(algorithm)

--Kobler signala til den opprinnelige komponenten.
port map (
clk => clk,
rst => reset,
enable_in => enable_in,
start => start,
enable => enable,
do_add => do_add,
do_subtract => do_subtract,
do_hold => do_hold,
data_in => data_in,
data_out => data_out);

--Deklarer komponenten alu_synt.
alu_synt : entity add_sub_alu_synth(structure)

--Kobler signala til den synthiserte komponenten.
port map (
clk => clk,
rst => reset,
enable_in => enable_in,
start => start,
enable => enable,
do_add => do_add,
do_subtract => do_subtract,
do_hold => do_hold,
data_in => data_in,
data_out => data_out_synt);

--Klokkegenerator
clock_gen : process
begin
clk <= '0', '1' after 50 ns;
wait for 100 ns;
end process clock_gen;

--Setter testvektorane.
reset <= '0', '1' after 60 ns;
enable <= '1', '0' after 900 ns;
enable_in <= '0', '1' after 400 ns;
start <= '1', '0' after 300 ns;
do_add <= '1', '0' after 660 ns;
do_subtract <= '0';
do_hold <= '0';
data_in <= X"3";

--Test process for å samanlikne utsignala kvart nanosekund.
test : process
begin
wait for 1 ns;
assert (data_out = data_out_synt)
report "Data ut er ulik"
severity Error;
end process test;

end;

</pre>

[[Category:Mikroelektronikk]]

Synthese av VHDL

2009-03-09T23:18:58Z

St12361: Undo revision 298 by St12361 (Talk)

===Synthesisering av vhdl kode===

Grunnen til at vi skal synthesisere koden, er at vi må lage beskrivelse av koden tilpassa ein krets.

Vi vil no prøve å synthesisere vhdl kode. Og etterpå vil vi lage ein testbenk der vi samanliknar utsignale frå den sythisierte og den opprinnelige koden. Vi bruker ein alu som eksempel.

==Precision==

<pre>
mentor
precision
</pre>

Pass på at lisensen for Quartus er korrekt satt opp, og at Precision finner Quartus.
Sett opp lisensen i Quartus ved å starte Quartus, og velg menyen

Precision er eit program som bruker Quartus til å synthisiere vhdl kode. For å starte opp dette skriv: presision i eit terminalvindu. Vel deretter New Project, og deretter Add input file(i dette tilfelle alu_example.vhdl). Så går vi inn på Setup design, velger ein kretsprodusent, den ønska kretsen og designfrekvens(i vårt tilfelle valgte vi Altera APEX 20KE med frekvens 200MHz). Trykk så compile, og synthesize. No kan vi sjå på den generte kretsen i RTL Schematic og Technology Schematic(syntese med den valgte kretsen).

Hvis du får en "ROOTDIR"-error, mangler det en variabel. Skriv følgende i terminalen:

<pre>
setenv QUARTUS_ROOTDIR /prog/quartus
</pre>

==Modelsim==

Start opp Modelsim, lag nytt prosjekt og legg til vhdl fila(alu_example.vhdl). Så legg vi til fila som Precision generte i prosjektdir til 'precision/prosjektnavn_temp_1/simulation/modelsim/prosjektnavn.vho' (i vårt tilfelle 'alu/add_sub_alu_temp_1/simulation/modelsim/add_sub_alu.vho').

Deretter legger vi til ei ny vhdl fil der vi skal lage testbenken vår. Vi legger til ein komponent av den opprinnelige og den synthesiserte vhdl koden. Vi koblar alle inngangane til samme signal på testbenken, og gir ut 2 forskjellige utsignal for å samanlikne ved hjelp av assert(sjå fila alu_tb.vhdl). Vi må ha ulike entitynavn på den synthesiserte og opprinnlige komponenten, ellers vil ikkje simuleringa virka. På grunn av at utsignala av dei to komponentane ikkje skifta heilt synkront, testa vi berre kvart nanosekund ved å putta assert inn i ein process med wait for 1ns:

<pre>
test : process
begin
wait for 1 ns;
assert (data_out = data_out_synt)
report "Data ut er ulik"
severity Error;
end process test;
</pre>

Når vi har laga testbenken, kompilerer vi(husk å kompilere i rett rekkefølge med compileorder->autogenerate) filene.

==Simulering med timing==

<pre>
vsim -t ps alu_tb -sdfmax :alu_tb:ali=/heim/yngve/vhdl/syntese/alu_temp_1/simulation/modelsim/add_sub_alu_vhd.sdo
</pre>

Vi kan sjå at i dei første 50 nanosekunda er utsignala ulike. Dette er fordi før første klokkeflanke er verdiane udefinert i den opprinnelige komponenten, medan den synthesisere ikkje kan ha udefinerte verdiar. I Modelsim vil vi derfor få ein del feilmeldingar dei første 50 nanosekunda.

==Konklusjon==

Vi kan teste om den synthesisere komponenten oppfører seg likt med den opprinnelige komponenten ved å koble begge to til samme testbenk. Vi fekk problem i overgangane når vi testa kontinuerlig, så vi løyste problemet ved å berre teste kvart naonosekund. Bortsett frå dei første 50 nanosekunda(sjå grunn over) kan vi sjå at begge komponetane gir ut samme utsignal. Vi prøvde å bruke samme enitynavn på begge komponentane med ulik arcitechture, men fekk berre lov å kompilere og ikkje simulere. Vi kan derfor konkludere med at desse må ha ulike navn.

==Kode==

===Kode til alu_example.vhdl===

<pre>
LIBRARY ieee;
USE ieee.std_logic_1164.All;
USE ieee.std_logic_unsigned.all;

ENTITY add_sub_alu IS
PORT (clk, rst : IN std_logic;
enable_in : IN std_logic;
start : IN std_logic;
enable : IN std_logic;
do_add : IN std_logic;
do_subtract : IN std_logic;
do_hold : IN std_logic;
data_in : IN std_logic_vector(3 DOWNTO 0);
data_out : OUT std_logic_vector (3 DOWNTO 0) BUS);
END add_sub_alu;

ARCHITECTURE algorithm OF add_sub_alu IS
TYPE states IS (hold, reset, add, subtract);
SIGNAL state_var : states;
SIGNAL reg, int_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL latched_data_in: std_logic_vector(3 DOWNTO 0);
BEGIN

latch: PROCESS (enable_in, data_in)is
BEGIN
IF (enable_in = '1') THEN
latched_data_in <= data_in;
END IF;
END PROCESS latch;

fsm: PROCESS (clk, rst) is
BEGIN
IF (rst = '0') THEN
state_var <= reset;
ELSIF rising_edge(clk) THEN
CASE state_var IS
WHEN hold => IF (start = '1') THEN
state_var <= reset;
END IF;
WHEN reset => IF (do_add = '1') THEN
state_var <= add;
ELSIF (do_subtract = '1') THEN
state_var <= subtract;
END IF;
WHEN add => IF (do_hold = '1') THEN
state_var <= hold;
ELSIF (do_subtract = '1') THEN
state_var <= subtract;
END IF;
WHEN subtract => IF (do_hold = '1') THEN
state_var <= hold;
ELSIF (do_add = '1') THEN
state_var <= add;
END IF;
WHEN OTHERS => state_var <= reset;
END CASE;
END IF;
END PROCESS fsm;

alu: PROCESS (state_var, latched_data_in, reg)is
BEGIN
CASE state_var IS
WHEN add => int_reg <= reg + latched_data_in;
WHEN subtract => int_reg <= reg - latched_data_in;
WHEN reset => int_reg <= "0000";
WHEN hold => int_reg <= reg;
WHEN OTHERS => int_reg <= reg;
END CASE;
END PROCESS alu;

mem: PROCESS (clk) is
BEGIN
IF (clk = '1' AND clk'LAST_VALUE = '0') THEN
reg <= int_reg;
END IF;
END PROCESS mem;

tri: PROCESS (enable, reg) is
BEGIN
FOR i IN 3 DOWNTO 0 LOOP
IF (enable = '1') THEN
data_out(i) <= reg(i);
ELSE
data_out(i) <= null;
END IF;
END LOOP;
END PROCESS tri;

END algorithm;
</pre>

===Koden til add_sub_alu.vho===

<pre>
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version"

-- DATE "02/18/2005 13:34:52"

--
-- Device: Altera EP20K200EQC208-1 Package PQFP208
--

--
-- This VHDL file should be used for MODELSIM (VHDL OUTPUT FROM QUARTUS II) only
--

LIBRARY IEEE, apex20ke;
USE IEEE.std_logic_1164.all;
USE apex20ke.apex20ke_components.all;

ENTITY add_sub_alu_synt IS
PORT (
enable : IN std_logic;
clk : IN std_logic;
do_hold : IN std_logic;
rst : IN std_logic;
do_add : IN std_logic;
do_subtract : IN std_logic;
enable_in : IN std_logic;
data_in : IN std_logic_vector(3 DOWNTO 0);
start : IN std_logic;
data_out : OUT std_logic_vector(3 DOWNTO 0)
);
END add_sub_alu_synt;

ARCHITECTURE structure OF add_sub_alu_synt IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL ww_enable : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_do_hold : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_do_add : std_logic;
SIGNAL ww_do_subtract : std_logic;
SIGNAL ww_enable_in : std_logic;
SIGNAL ww_data_in : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_start : std_logic;
SIGNAL ww_data_out : std_logic_vector(3 DOWNTO 0);
SIGNAL if0a5x13_aCOMBOUT : std_logic;
SIGNAL start_acombout : std_logic;
SIGNAL data_in_a2_a_acombout : std_logic;
SIGNAL do_subtract_acombout : std_logic;
SIGNAL do_hold_acombout : std_logic;
SIGNAL n5831x3 : std_logic;
SIGNAL do_add_acombout : std_logic;
SIGNAL n5831x2 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL rst_acombout : std_logic;
SIGNAL n544cx3 : std_logic;
SIGNAL n544cx2 : std_logic;
SIGNAL state_var_1 : std_logic;
SIGNAL data_in_a0_a_acombout : std_logic;
SIGNAL enable_in_acombout : std_logic;
SIGNAL latched_data_in_0 : std_logic;
SIGNAL nfc54x2 : std_logic;
SIGNAL cin : std_logic;
SIGNAL a_2_dup_240 : std_logic;
SIGNAL nf0a5x2 : std_logic;
SIGNAL reg_0 : std_logic;
SIGNAL enable_acombout : std_logic;
SIGNAL data_in_a1_a_acombout : std_logic;
SIGNAL latched_data_in_1 : std_logic;
SIGNAL nf0a5x8 : std_logic;
SIGNAL nf0a5x10 : std_logic;
SIGNAL nf0a5x9 : std_logic;
SIGNAL a_2_dup_239 : std_logic;
SIGNAL reg_1 : std_logic;
SIGNAL latched_data_in_2 : std_logic;
SIGNAL nf0a5x6 : std_logic;
SIGNAL nf0a5x7 : std_logic;
SIGNAL a_2_dup_238 : std_logic;
SIGNAL reg_2 : std_logic;
SIGNAL data_in_a3_a_acombout : std_logic;
SIGNAL latched_data_in_3 : std_logic;
SIGNAL nf0a5x4 : std_logic;
SIGNAL nf0a5x5 : std_logic;
SIGNAL a_2 : std_logic;
SIGNAL reg_3 : std_logic;
SIGNAL ALT_INV_rst_acombout : std_logic;

BEGIN

ww_enable <= enable;
ww_clk <= clk;
ww_do_hold <= do_hold;
ww_rst <= rst;
ww_do_add <= do_add;
ww_do_subtract <= do_subtract;
ww_enable_in <= enable_in;
ww_data_in <= data_in;
ww_start <= start;
data_out <= ww_data_out;
ALT_INV_rst_acombout <= NOT rst_acombout;

start_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_start,
combout => start_acombout);

data_in_ibuf_2 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(2),
combout => data_in_a2_a_acombout);

do_subtract_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_subtract,
combout => do_subtract_acombout);

do_hold_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_hold,
combout => do_hold_acombout);

ib0e1x3 : apex20ke_lcell
-- Equation(s):
-- n5831x3 = do_hold_acombout & state_var_1

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datac => do_hold_acombout,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n5831x3);

do_add_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_add,
combout => do_add_acombout);

ib0e1x2 : apex20ke_lcell
-- Equation(s):
-- n5831x2 = n544cx3 & state_var_1 & !do_subtract_acombout # !state_var_1 & !start_acombout

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "3050",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => start_acombout,
datab => do_subtract_acombout,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n5831x2);

clk_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_clk,
combout => clk_acombout);

rst_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_rst,
combout => rst_acombout);

reg_state_var_0 : apex20ke_lcell
-- Equation(s):
-- n544cx3 = DFFE(n5831x3 # n5831x2 # !n544cx3 & do_add_acombout, GLOBAL(clk_acombout), GLOBAL(rst_acombout), , )

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FFDC",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
dataa => n544cx3,
datab => n5831x3,
datac => do_add_acombout,
datad => n5831x2,
clk => clk_acombout,
aclr => ALT_INV_rst_acombout,
devclrn => devclrn,
devpor => devpor,
regout => n544cx3);

ib0e2x3 : apex20ke_lcell
-- Equation(s):
-- n544cx2 = !n544cx3 & !state_var_1 & do_add_acombout # do_subtract_acombout

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "000E",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => do_add_acombout,
datab => do_subtract_acombout,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n544cx2);

reg_state_var_1 : apex20ke_lcell
-- Equation(s):
-- state_var_1 = DFFE(n544cx2 # !do_hold_acombout & state_var_1, GLOBAL(clk_acombout), GLOBAL(rst_acombout), , )

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FF50",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
dataa => do_hold_acombout,
datac => state_var_1,
datad => n544cx2,
clk => clk_acombout,
aclr => ALT_INV_rst_acombout,
devclrn => devclrn,
devpor => devpor,
regout => state_var_1);

data_in_ibuf_0 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(0),
combout => data_in_a0_a_acombout);

enable_in_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_enable_in,
combout => enable_in_acombout);

id8dfx3 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_0 = enable_in_acombout & data_in_a0_a_acombout # !enable_in_acombout & latched_data_in_0

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CACA",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => latched_data_in_0,
datab => data_in_a0_a_acombout,
datac => enable_in_acombout,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_0);

id8dfx2 : apex20ke_lcell
-- Equation(s):
-- nfc54x2 = latched_data_in_0 $ (!n544cx3 # !state_var_1)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C30F",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datac => latched_data_in_0,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nfc54x2);

id8dfx1 : apex20ke_lcell
-- Equation(s):
-- cin = state_var_1 & !n544cx3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "00CC",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => cin);

ifc54x2 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_240 = nfc54x2 $ reg_0 $ cin

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C33C",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => nfc54x2,
datac => reg_0,
datad => cin,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_240);

i197dx1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x2 = state_var_1 # !n544cx3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CCFF",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x2);

reg_reg_0 : apex20ke_lcell
-- Equation(s):
-- reg_0 = DFFE(a_2_dup_240 & state_var_1, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => a_2_dup_240,
datad => state_var_1,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_0);

enable_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_enable,
combout => enable_acombout);

data_in_ibuf_1 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(1),
combout => data_in_a1_a_acombout);

i2456x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_1 = enable_in_acombout & data_in_a1_a_acombout # !enable_in_acombout & latched_data_in_1

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CFC0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => data_in_a1_a_acombout,
datac => enable_in_acombout,
datad => latched_data_in_1,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_1);

i2456x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x8 = latched_data_in_1 $ (!state_var_1 # !n544cx3)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C333",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => latched_data_in_1,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x8);

if0a5x14 : apex20ke_lcell
-- Equation(s):
-- nf0a5x10 = reg_0 & nfc54x2 # cin # !reg_0 & nfc54x2 & cin

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FCC0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => reg_0,
datac => nfc54x2,
datad => cin,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x10);

if0a5x13 : apex20ke_lcell
-- Equation(s):
-- nf0a5x9 = CARRY(nf0a5x10)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
packed_mode => "false",
lut_mask => "00CC",
output_mode => "none")
-- pragma translate_on
PORT MAP (
datab => nf0a5x10,
devclrn => devclrn,
devpor => devpor,
cout => nf0a5x9);

if0a5x10 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_239 = reg_1 $ nf0a5x8 $ nf0a5x9
-- nf0a5x7 = CARRY(reg_1 & !nf0a5x8 & !nf0a5x9 # !reg_1 & !nf0a5x9 # !nf0a5x8)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "9617",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_1,
datab => nf0a5x8,
cin => nf0a5x9,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_239,
cout => nf0a5x7);

reg_reg_1 : apex20ke_lcell
-- Equation(s):
-- reg_1 = DFFE(state_var_1 & a_2_dup_239, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2_dup_239,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_1);

ia9f8x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_2 = enable_in_acombout & data_in_a2_a_acombout # !enable_in_acombout & latched_data_in_2

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "AFA0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => data_in_a2_a_acombout,
datac => enable_in_acombout,
datad => latched_data_in_2,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_2);

ia9f8x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x6 = latched_data_in_2 $ (!state_var_1 # !n544cx3)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C333",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => latched_data_in_2,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x6);

if0a5x7 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_238 = reg_2 $ nf0a5x6 $ !nf0a5x7
-- nf0a5x5 = CARRY(reg_2 & nf0a5x6 # !nf0a5x7 # !reg_2 & nf0a5x6 & !nf0a5x7)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "698E",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_2,
datab => nf0a5x6,
cin => nf0a5x7,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_238,
cout => nf0a5x5);

reg_reg_2 : apex20ke_lcell
-- Equation(s):
-- reg_2 = DFFE(state_var_1 & a_2_dup_238, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2_dup_238,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_2);

data_in_ibuf_3 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(3),
combout => data_in_a3_a_acombout);

ia9f5x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_3 = enable_in_acombout & data_in_a3_a_acombout # !enable_in_acombout & latched_data_in_3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F5A0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => enable_in_acombout,
datac => data_in_a3_a_acombout,
datad => latched_data_in_3,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_3);

ia9f5x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x4 = latched_data_in_3 $ (!n544cx3 # !state_var_1)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C30F",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datac => latched_data_in_3,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x4);

if0a5x4 : apex20ke_lcell
-- Equation(s):
-- a_2 = reg_3 $ (nf0a5x5 $ nf0a5x4)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
cin_used => "true",
packed_mode => "false",
lut_mask => "A55A",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_3,
datad => nf0a5x4,
cin => nf0a5x5,
devclrn => devclrn,
devpor => devpor,
combout => a_2);

reg_reg_3 : apex20ke_lcell
-- Equation(s):
-- reg_3 = DFFE(state_var_1 & a_2, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_3);

tri_data_out_0 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_0,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(0));

tri_data_out_1 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_1,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(1));

tri_data_out_2 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_2,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(2));

tri_data_out_3 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_3,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(3));
END structure;

</pre>

===Koden til alu_tb.vhdl===

<pre>
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;

entity alu_tb is
end entity alu_tb;

architecture struct of alu_tb is
--Deklaring av signal som skal koblast til komponentane.
--Alle innsignal er felles, medan vi har 2 forskjellige utsignal.
signal clk, reset : std_logic;
signal enable_in : std_logic;
signal start : std_logic;
signal enable : std_logic;
signal do_add : std_logic;
signal do_subtract : std_logic;
signal do_hold : std_logic;
signal data_in : std_logic_vector(3 downto 0);
signal data_out : std_logic_vector(3 downto 0);
signal data_out_synt : std_logic_vector(3 downto 0);

begin

--Deklarer komponenten alu.
alu : entity add_sub_alu(algorithm)

--Kobler signala til den opprinnelige komponenten.
port map (
clk => clk,
rst => reset,
enable_in => enable_in,
start => start,
enable => enable,
do_add => do_add,
do_subtract => do_subtract,
do_hold => do_hold,
data_in => data_in,
data_out => data_out);

--Deklarer komponenten alu_synt.
alu_synt : entity add_sub_alu_synth(structure)

--Kobler signala til den synthiserte komponenten.
port map (
clk => clk,
rst => reset,
enable_in => enable_in,
start => start,
enable => enable,
do_add => do_add,
do_subtract => do_subtract,
do_hold => do_hold,
data_in => data_in,
data_out => data_out_synt);

--Klokkegenerator
clock_gen : process
begin
clk <= '0', '1' after 50 ns;
wait for 100 ns;
end process clock_gen;

--Setter testvektorane.
reset <= '0', '1' after 60 ns;
enable <= '1', '0' after 900 ns;
enable_in <= '0', '1' after 400 ns;
start <= '1', '0' after 300 ns;
do_add <= '1', '0' after 660 ns;
do_subtract <= '0';
do_hold <= '0';
data_in <= X"3";

--Test process for å samanlikne utsignala kvart nanosekund.
test : process
begin
wait for 1 ns;
assert (data_out = data_out_synt)
report "Data ut er ulik"
severity Error;
end process test;

end;

</pre>

Synthese av VHDL

2009-03-09T23:17:04Z

St12361: corrected entity reference for alu_tb

===Synthesisering av vhdl kode===

Grunnen til at vi skal synthesisere koden, er at vi må lage beskrivelse av koden tilpassa ein krets.

Vi vil no prøve å synthesisere vhdl kode. Og etterpå vil vi lage ein testbenk der vi samanliknar utsignale frå den sythisierte og den opprinnelige koden. Vi bruker ein alu som eksempel.

==Precision==

<pre>
mentor
precision
</pre>

Pass på at lisensen for Quartus er korrekt satt opp, og at Precision finner Quartus.
Sett opp lisensen i Quartus ved å starte Quartus, og velg menyen

Precision er eit program som bruker Quartus til å synthisiere vhdl kode. For å starte opp dette skriv: presision i eit terminalvindu. Vel deretter New Project, og deretter Add input file(i dette tilfelle alu_example.vhdl). Så går vi inn på Setup design, velger ein kretsprodusent, den ønska kretsen og designfrekvens(i vårt tilfelle valgte vi Altera APEX 20KE med frekvens 200MHz). Trykk så compile, og synthesize. No kan vi sjå på den generte kretsen i RTL Schematic og Technology Schematic(syntese med den valgte kretsen).

Hvis du får en "ROOTDIR"-error, mangler det en variabel. Skriv følgende i terminalen:

<pre>
setenv QUARTUS_ROOTDIR /prog/quartus
</pre>

==Modelsim==

Start opp Modelsim, lag nytt prosjekt og legg til vhdl fila(alu_example.vhdl). Så legg vi til fila som Precision generte i prosjektdir til 'precision/prosjektnavn_temp_1/simulation/modelsim/prosjektnavn.vho' (i vårt tilfelle 'alu/add_sub_alu_temp_1/simulation/modelsim/add_sub_alu.vho').

Deretter legger vi til ei ny vhdl fil der vi skal lage testbenken vår. Vi legger til ein komponent av den opprinnelige og den synthesiserte vhdl koden. Vi koblar alle inngangane til samme signal på testbenken, og gir ut 2 forskjellige utsignal for å samanlikne ved hjelp av assert(sjå fila alu_tb.vhdl). Vi må ha ulike entitynavn på den synthesiserte og opprinnlige komponenten, ellers vil ikkje simuleringa virka. På grunn av at utsignala av dei to komponentane ikkje skifta heilt synkront, testa vi berre kvart nanosekund ved å putta assert inn i ein process med wait for 1ns:

<pre>
test : process
begin
wait for 1 ns;
assert (data_out = data_out_synt)
report "Data ut er ulik"
severity Error;
end process test;
</pre>

Når vi har laga testbenken, kompilerer vi(husk å kompilere i rett rekkefølge med compileorder->autogenerate) filene.

==Simulering med timing==

<pre>
vsim -t ps alu_tb -sdfmax :alu_tb:ali=/heim/yngve/vhdl/syntese/alu_temp_1/simulation/modelsim/add_sub_alu_vhd.sdo
</pre>

Vi kan sjå at i dei første 50 nanosekunda er utsignala ulike. Dette er fordi før første klokkeflanke er verdiane udefinert i den opprinnelige komponenten, medan den synthesisere ikkje kan ha udefinerte verdiar. I Modelsim vil vi derfor få ein del feilmeldingar dei første 50 nanosekunda.

==Konklusjon==

Vi kan teste om den synthesisere komponenten oppfører seg likt med den opprinnelige komponenten ved å koble begge to til samme testbenk. Vi fekk problem i overgangane når vi testa kontinuerlig, så vi løyste problemet ved å berre teste kvart naonosekund. Bortsett frå dei første 50 nanosekunda(sjå grunn over) kan vi sjå at begge komponetane gir ut samme utsignal. Vi prøvde å bruke samme enitynavn på begge komponentane med ulik arcitechture, men fekk berre lov å kompilere og ikkje simulere. Vi kan derfor konkludere med at desse må ha ulike navn.

==Kode==

===Kode til alu_example.vhdl===

<pre>
LIBRARY ieee;
USE ieee.std_logic_1164.All;
USE ieee.std_logic_unsigned.all;

ENTITY add_sub_alu IS
PORT (clk, rst : IN std_logic;
enable_in : IN std_logic;
start : IN std_logic;
enable : IN std_logic;
do_add : IN std_logic;
do_subtract : IN std_logic;
do_hold : IN std_logic;
data_in : IN std_logic_vector(3 DOWNTO 0);
data_out : OUT std_logic_vector (3 DOWNTO 0) BUS);
END add_sub_alu;

ARCHITECTURE algorithm OF add_sub_alu IS
TYPE states IS (hold, reset, add, subtract);
SIGNAL state_var : states;
SIGNAL reg, int_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL latched_data_in: std_logic_vector(3 DOWNTO 0);
BEGIN

latch: PROCESS (enable_in, data_in)is
BEGIN
IF (enable_in = '1') THEN
latched_data_in <= data_in;
END IF;
END PROCESS latch;

fsm: PROCESS (clk, rst) is
BEGIN
IF (rst = '0') THEN
state_var <= reset;
ELSIF rising_edge(clk) THEN
CASE state_var IS
WHEN hold => IF (start = '1') THEN
state_var <= reset;
END IF;
WHEN reset => IF (do_add = '1') THEN
state_var <= add;
ELSIF (do_subtract = '1') THEN
state_var <= subtract;
END IF;
WHEN add => IF (do_hold = '1') THEN
state_var <= hold;
ELSIF (do_subtract = '1') THEN
state_var <= subtract;
END IF;
WHEN subtract => IF (do_hold = '1') THEN
state_var <= hold;
ELSIF (do_add = '1') THEN
state_var <= add;
END IF;
WHEN OTHERS => state_var <= reset;
END CASE;
END IF;
END PROCESS fsm;

alu: PROCESS (state_var, latched_data_in, reg)is
BEGIN
CASE state_var IS
WHEN add => int_reg <= reg + latched_data_in;
WHEN subtract => int_reg <= reg - latched_data_in;
WHEN reset => int_reg <= "0000";
WHEN hold => int_reg <= reg;
WHEN OTHERS => int_reg <= reg;
END CASE;
END PROCESS alu;

mem: PROCESS (clk) is
BEGIN
IF (clk = '1' AND clk'LAST_VALUE = '0') THEN
reg <= int_reg;
END IF;
END PROCESS mem;

tri: PROCESS (enable, reg) is
BEGIN
FOR i IN 3 DOWNTO 0 LOOP
IF (enable = '1') THEN
data_out(i) <= reg(i);
ELSE
data_out(i) <= null;
END IF;
END LOOP;
END PROCESS tri;

END algorithm;
</pre>

===Koden til add_sub_alu.vho===

<pre>
-- Copyright (C) 1991-2005 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version"

-- DATE "02/18/2005 13:34:52"

--
-- Device: Altera EP20K200EQC208-1 Package PQFP208
--

--
-- This VHDL file should be used for MODELSIM (VHDL OUTPUT FROM QUARTUS II) only
--

LIBRARY IEEE, apex20ke;
USE IEEE.std_logic_1164.all;
USE apex20ke.apex20ke_components.all;

ENTITY add_sub_alu_synt IS
PORT (
enable : IN std_logic;
clk : IN std_logic;
do_hold : IN std_logic;
rst : IN std_logic;
do_add : IN std_logic;
do_subtract : IN std_logic;
enable_in : IN std_logic;
data_in : IN std_logic_vector(3 DOWNTO 0);
start : IN std_logic;
data_out : OUT std_logic_vector(3 DOWNTO 0)
);
END add_sub_alu_synt;

ARCHITECTURE structure OF add_sub_alu_synt IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL ww_enable : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_do_hold : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_do_add : std_logic;
SIGNAL ww_do_subtract : std_logic;
SIGNAL ww_enable_in : std_logic;
SIGNAL ww_data_in : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_start : std_logic;
SIGNAL ww_data_out : std_logic_vector(3 DOWNTO 0);
SIGNAL if0a5x13_aCOMBOUT : std_logic;
SIGNAL start_acombout : std_logic;
SIGNAL data_in_a2_a_acombout : std_logic;
SIGNAL do_subtract_acombout : std_logic;
SIGNAL do_hold_acombout : std_logic;
SIGNAL n5831x3 : std_logic;
SIGNAL do_add_acombout : std_logic;
SIGNAL n5831x2 : std_logic;
SIGNAL clk_acombout : std_logic;
SIGNAL rst_acombout : std_logic;
SIGNAL n544cx3 : std_logic;
SIGNAL n544cx2 : std_logic;
SIGNAL state_var_1 : std_logic;
SIGNAL data_in_a0_a_acombout : std_logic;
SIGNAL enable_in_acombout : std_logic;
SIGNAL latched_data_in_0 : std_logic;
SIGNAL nfc54x2 : std_logic;
SIGNAL cin : std_logic;
SIGNAL a_2_dup_240 : std_logic;
SIGNAL nf0a5x2 : std_logic;
SIGNAL reg_0 : std_logic;
SIGNAL enable_acombout : std_logic;
SIGNAL data_in_a1_a_acombout : std_logic;
SIGNAL latched_data_in_1 : std_logic;
SIGNAL nf0a5x8 : std_logic;
SIGNAL nf0a5x10 : std_logic;
SIGNAL nf0a5x9 : std_logic;
SIGNAL a_2_dup_239 : std_logic;
SIGNAL reg_1 : std_logic;
SIGNAL latched_data_in_2 : std_logic;
SIGNAL nf0a5x6 : std_logic;
SIGNAL nf0a5x7 : std_logic;
SIGNAL a_2_dup_238 : std_logic;
SIGNAL reg_2 : std_logic;
SIGNAL data_in_a3_a_acombout : std_logic;
SIGNAL latched_data_in_3 : std_logic;
SIGNAL nf0a5x4 : std_logic;
SIGNAL nf0a5x5 : std_logic;
SIGNAL a_2 : std_logic;
SIGNAL reg_3 : std_logic;
SIGNAL ALT_INV_rst_acombout : std_logic;

BEGIN

ww_enable <= enable;
ww_clk <= clk;
ww_do_hold <= do_hold;
ww_rst <= rst;
ww_do_add <= do_add;
ww_do_subtract <= do_subtract;
ww_enable_in <= enable_in;
ww_data_in <= data_in;
ww_start <= start;
data_out <= ww_data_out;
ALT_INV_rst_acombout <= NOT rst_acombout;

start_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_start,
combout => start_acombout);

data_in_ibuf_2 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(2),
combout => data_in_a2_a_acombout);

do_subtract_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_subtract,
combout => do_subtract_acombout);

do_hold_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_hold,
combout => do_hold_acombout);

ib0e1x3 : apex20ke_lcell
-- Equation(s):
-- n5831x3 = do_hold_acombout & state_var_1

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datac => do_hold_acombout,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n5831x3);

do_add_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_do_add,
combout => do_add_acombout);

ib0e1x2 : apex20ke_lcell
-- Equation(s):
-- n5831x2 = n544cx3 & state_var_1 & !do_subtract_acombout # !state_var_1 & !start_acombout

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "3050",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => start_acombout,
datab => do_subtract_acombout,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n5831x2);

clk_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_clk,
combout => clk_acombout);

rst_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_rst,
combout => rst_acombout);

reg_state_var_0 : apex20ke_lcell
-- Equation(s):
-- n544cx3 = DFFE(n5831x3 # n5831x2 # !n544cx3 & do_add_acombout, GLOBAL(clk_acombout), GLOBAL(rst_acombout), , )

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FFDC",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
dataa => n544cx3,
datab => n5831x3,
datac => do_add_acombout,
datad => n5831x2,
clk => clk_acombout,
aclr => ALT_INV_rst_acombout,
devclrn => devclrn,
devpor => devpor,
regout => n544cx3);

ib0e2x3 : apex20ke_lcell
-- Equation(s):
-- n544cx2 = !n544cx3 & !state_var_1 & do_add_acombout # do_subtract_acombout

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "000E",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => do_add_acombout,
datab => do_subtract_acombout,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => n544cx2);

reg_state_var_1 : apex20ke_lcell
-- Equation(s):
-- state_var_1 = DFFE(n544cx2 # !do_hold_acombout & state_var_1, GLOBAL(clk_acombout), GLOBAL(rst_acombout), , )

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FF50",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
dataa => do_hold_acombout,
datac => state_var_1,
datad => n544cx2,
clk => clk_acombout,
aclr => ALT_INV_rst_acombout,
devclrn => devclrn,
devpor => devpor,
regout => state_var_1);

data_in_ibuf_0 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(0),
combout => data_in_a0_a_acombout);

enable_in_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_enable_in,
combout => enable_in_acombout);

id8dfx3 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_0 = enable_in_acombout & data_in_a0_a_acombout # !enable_in_acombout & latched_data_in_0

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CACA",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => latched_data_in_0,
datab => data_in_a0_a_acombout,
datac => enable_in_acombout,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_0);

id8dfx2 : apex20ke_lcell
-- Equation(s):
-- nfc54x2 = latched_data_in_0 $ (!n544cx3 # !state_var_1)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C30F",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datac => latched_data_in_0,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nfc54x2);

id8dfx1 : apex20ke_lcell
-- Equation(s):
-- cin = state_var_1 & !n544cx3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "00CC",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => cin);

ifc54x2 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_240 = nfc54x2 $ reg_0 $ cin

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C33C",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => nfc54x2,
datac => reg_0,
datad => cin,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_240);

i197dx1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x2 = state_var_1 # !n544cx3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CCFF",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x2);

reg_reg_0 : apex20ke_lcell
-- Equation(s):
-- reg_0 = DFFE(a_2_dup_240 & state_var_1, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => a_2_dup_240,
datad => state_var_1,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_0);

enable_ibuf : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_enable,
combout => enable_acombout);

data_in_ibuf_1 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(1),
combout => data_in_a1_a_acombout);

i2456x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_1 = enable_in_acombout & data_in_a1_a_acombout # !enable_in_acombout & latched_data_in_1

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "CFC0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => data_in_a1_a_acombout,
datac => enable_in_acombout,
datad => latched_data_in_1,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_1);

i2456x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x8 = latched_data_in_1 $ (!state_var_1 # !n544cx3)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C333",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => latched_data_in_1,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x8);

if0a5x14 : apex20ke_lcell
-- Equation(s):
-- nf0a5x10 = reg_0 & nfc54x2 # cin # !reg_0 & nfc54x2 & cin

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "FCC0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => reg_0,
datac => nfc54x2,
datad => cin,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x10);

if0a5x13 : apex20ke_lcell
-- Equation(s):
-- nf0a5x9 = CARRY(nf0a5x10)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
packed_mode => "false",
lut_mask => "00CC",
output_mode => "none")
-- pragma translate_on
PORT MAP (
datab => nf0a5x10,
devclrn => devclrn,
devpor => devpor,
cout => nf0a5x9);

if0a5x10 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_239 = reg_1 $ nf0a5x8 $ nf0a5x9
-- nf0a5x7 = CARRY(reg_1 & !nf0a5x8 & !nf0a5x9 # !reg_1 & !nf0a5x9 # !nf0a5x8)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "9617",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_1,
datab => nf0a5x8,
cin => nf0a5x9,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_239,
cout => nf0a5x7);

reg_reg_1 : apex20ke_lcell
-- Equation(s):
-- reg_1 = DFFE(state_var_1 & a_2_dup_239, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2_dup_239,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_1);

ia9f8x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_2 = enable_in_acombout & data_in_a2_a_acombout # !enable_in_acombout & latched_data_in_2

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "AFA0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => data_in_a2_a_acombout,
datac => enable_in_acombout,
datad => latched_data_in_2,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_2);

ia9f8x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x6 = latched_data_in_2 $ (!state_var_1 # !n544cx3)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C333",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => latched_data_in_2,
datac => n544cx3,
datad => state_var_1,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x6);

if0a5x7 : apex20ke_lcell
-- Equation(s):
-- a_2_dup_238 = reg_2 $ nf0a5x6 $ !nf0a5x7
-- nf0a5x5 = CARRY(reg_2 & nf0a5x6 # !nf0a5x7 # !reg_2 & nf0a5x6 & !nf0a5x7)

-- pragma translate_off
GENERIC MAP (
operation_mode => "arithmetic",
cin_used => "true",
packed_mode => "false",
lut_mask => "698E",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_2,
datab => nf0a5x6,
cin => nf0a5x7,
devclrn => devclrn,
devpor => devpor,
combout => a_2_dup_238,
cout => nf0a5x5);

reg_reg_2 : apex20ke_lcell
-- Equation(s):
-- reg_2 = DFFE(state_var_1 & a_2_dup_238, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2_dup_238,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_2);

data_in_ibuf_3 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "input",
reg_source_mode => "none",
feedback_mode => "from_pin",
power_up => "low")
-- pragma translate_on
PORT MAP (
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
oe => GND,
ena => VCC,
padio => ww_data_in(3),
combout => data_in_a3_a_acombout);

ia9f5x2 : apex20ke_lcell
-- Equation(s):
-- latched_data_in_3 = enable_in_acombout & data_in_a3_a_acombout # !enable_in_acombout & latched_data_in_3

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F5A0",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => enable_in_acombout,
datac => data_in_a3_a_acombout,
datad => latched_data_in_3,
devclrn => devclrn,
devpor => devpor,
combout => latched_data_in_3);

ia9f5x1 : apex20ke_lcell
-- Equation(s):
-- nf0a5x4 = latched_data_in_3 $ (!n544cx3 # !state_var_1)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "C30F",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
datab => state_var_1,
datac => latched_data_in_3,
datad => n544cx3,
devclrn => devclrn,
devpor => devpor,
combout => nf0a5x4);

if0a5x4 : apex20ke_lcell
-- Equation(s):
-- a_2 = reg_3 $ (nf0a5x5 $ nf0a5x4)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
cin_used => "true",
packed_mode => "false",
lut_mask => "A55A",
output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
dataa => reg_3,
datad => nf0a5x4,
cin => nf0a5x5,
devclrn => devclrn,
devpor => devpor,
combout => a_2);

reg_reg_3 : apex20ke_lcell
-- Equation(s):
-- reg_3 = DFFE(state_var_1 & a_2, GLOBAL(clk_acombout), , , nf0a5x2)

-- pragma translate_off
GENERIC MAP (
operation_mode => "normal",
packed_mode => "false",
lut_mask => "F000",
output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
datac => state_var_1,
datad => a_2,
clk => clk_acombout,
ena => nf0a5x2,
devclrn => devclrn,
devpor => devpor,
regout => reg_3);

tri_data_out_0 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_0,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(0));

tri_data_out_1 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_1,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(1));

tri_data_out_2 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_2,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(2));

tri_data_out_3 : apex20ke_io
-- pragma translate_off
GENERIC MAP (
operation_mode => "output",
reg_source_mode => "none",
feedback_mode => "none",
power_up => "low")
-- pragma translate_on
PORT MAP (
datain => reg_3,
oe => enable_acombout,
devclrn => devclrn,
devpor => devpor,
devoe => devoe,
ena => VCC,
padio => ww_data_out(3));
END structure;

</pre>

===Koden til alu_tb.vhdl===

<pre>
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.all;

entity alu_tb is
end entity alu_tb;

architecture struct of alu_tb is
--Deklaring av signal som skal koblast til komponentane.
--Alle innsignal er felles, medan vi har 2 forskjellige utsignal.
signal clk, reset : std_logic;
signal enable_in : std_logic;
signal start : std_logic;
signal enable : std_logic;
signal do_add : std_logic;
signal do_subtract : std_logic;
signal do_hold : std_logic;
signal data_in : std_logic_vector(3 downto 0);
signal data_out : std_logic_vector(3 downto 0);
signal data_out_synt : std_logic_vector(3 downto 0);

begin

--Deklarer komponenten alu.
alu : entity add_sub_alu(algorithm)

--Kobler signala til den opprinnelige komponenten.
port map (
clk => clk,
rst => reset,
enable_in => enable_in,
start => start,
enable => enable,
do_add => do_add,
do_subtract => do_subtract,
do_hold => do_hold,
data_in => data_in,
data_out => data_out);

--Deklarer komponenten alu_synt.
alu_synt : entity add_sub_alu(structure)

--Kobler signala til den synthiserte komponenten.
port map (
clk => clk,
rst => reset,
enable_in => enable_in,
start => start,
enable => enable,
do_add => do_add,
do_subtract => do_subtract,
do_hold => do_hold,
data_in => data_in,
data_out => data_out_synt);

--Klokkegenerator
clock_gen : process
begin
clk <= '0', '1' after 50 ns;
wait for 100 ns;
end process clock_gen;

--Setter testvektorane.
reset <= '0', '1' after 60 ns;
enable <= '1', '0' after 900 ns;
enable_in <= '0', '1' after 400 ns;
start <= '1', '0' after 300 ns;
do_add <= '1', '0' after 660 ns;
do_subtract <= '0';
do_hold <= '0';
data_in <= X"3";

--Test process for å samanlikne utsignala kvart nanosekund.
test : process
begin
wait for 1 ns;
assert (data_out = data_out_synt)
report "Data ut er ulik"
severity Error;
end process test;

end;

</pre>

CAEN 40CH HV PSU

2009-03-06T13:26:09Z

St12361:

This how to is based on using the functionality of the custome Labview VI's. Refer to the User Manual for using the Terminal interface of the unit.

=== RS 232-Setting ===

Baud Rate: 9600
Parity: None
Data Bits: 8
Stop Bits: 1
Flow Control: None

Kladd

min. write time between commands: 60ms (30 ms worst case)

Bytes recieved (From top Menu @ 9600 bauds)
"1": 256 bytes (220 ms)
"1+b": 170 bytes (150 ms)
"1+b+a": 273 bytes (230 ms)
"1+b+a+n": 272 bytes (230 ms)
"1+b+a+c/i/j..": 14 bytes (15 ms)
"1+b+a+c/i/j..+X": 1 bytes (1 ms)
"1+b+a+c/i/j..+X+/r/n": 272 bytes (230 ms)

CAEN 40CH HV PSU

2009-03-03T14:00:07Z

St12361: New page: This how to is based on using the functionality of the custome Labview VI's. Refer to the User Manual for using the Terminal interface of the unit. === RS 232-Setting === Baud Rate: ...

Lab Equipment

2009-03-03T13:21:22Z

St12361: New page: {| border="1" cellpadding="5" cellspacing="0" !Equipment Name !Description !How To's |- |CAEN 40 Channel High Voltage System |High Voltage DC power supply equipped with 4x POS 200V, 4x NEG...

{| border="1" cellpadding="5" cellspacing="0"
!Equipment Name
!Description
!How To's
|-
|CAEN 40 Channel High Voltage System
|High Voltage DC power supply equipped with 4x POS 200V, 4x NEG 200V, 4x POS 2000V and 2 x POS 15 kV outputs
|[[CAEN 40CH HV PSU]]
|-

|}

Detector lab

2009-03-03T13:12:33Z

St12361:

== Goal ==
The aim of our research is to study high energy particle detectors, and to develop new detectors for the future. In particular, we are interested in studying medical applications of these detectors and to help bridge fundamental with technological research.

== Our projects ==
* [[PET Project]]
* [[Calorimeter Activities]]
* [[3D Detector Activities]]

== Who are we? ==
* Students: Hege, Kristine, Njål, Stian, Lars-Halvard, Andreas
* Postdoctors: Heidi
* Professors: Gerald, Bjarne, Dieter, Renate, [http://www.uib.no/personer/Kjetil.Ullaland Kjetil]
* Engineers: [http://www.uib.no/personer/Dominik.Fehlker Dominik], Werner, Kåre

== Where are we? ==
* The laboratory is situated in the 3rd floor at the IFT, room 332.

== Lab Equipment ==
Lab equipment list, how to's, equipment service log's etc...
* [[Lab Equipment]]

== Recent talks ==
3.2.2009:
* [http://web.ift.uib.no/~dominik/files/detectorlabwiki/talks/axialpet.ppt Dominik: MAPD/MPPC Characterization & Axial PET]
* Hege ...

Detector lab

2009-03-03T13:11:33Z

St12361:

== Goal ==
The aim of our research is to study high energy particle detectors, and to develop new detectors for the future. In particular, we are interested in studying medical applications of these detectors and to help bridge fundamental with technological research.

== Our projects ==
* [[PET Project]]
* [[Calorimeter Activities]]
* [[3D Detector Activities]]

== Who are we? ==
* Students: Hege, Kristine, Njål, Stian, Lars-Halvard, Andreas
* Postdoctors: Heidi
* Professors: Gerald, Bjarne, Dieter, Renate, [http://www.uib.no/personer/Kjetil.Ullaland Kjetil]
* Engineers: [http://www.uib.no/personer/Dominik.Fehlker Dominik], Werner, Kåre

== Where are we? ==
* The laboratory is situated in the 3rd floor at the IFT, room 332.

== Lab Equipment ==
List of lab equipment, how to's and service log's etc...
* [[Lab Equipment]]

== Recent talks ==
3.2.2009:
* [http://web.ift.uib.no/~dominik/files/detectorlabwiki/talks/axialpet.ppt Dominik: MAPD/MPPC Characterization & Axial PET]
* Hege ...

User talk:St12361

2009-03-03T12:31:49Z

St12361: New page: === RS 232-Setting === Baud Rate: 9600 Parity: None Data Bits: 8 Stop Bits: 1 Flow Control: None

=== RS 232-Setting ===

Baud Rate: 9600
Parity: None
Data Bits: 8
Stop Bits: 1
Flow Control: None

Photomultipliers

2009-02-25T14:19:08Z

St12361:

==Critical Parameters==

{| border="1" cellpadding="5" cellspacing="0"
!Parameter
!Description
!Typical Value (Fast PTM)
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
 

[[Image:PMT_Parameters.jpg]]

==Overview of different PMT's==
{| border="1" cellpadding="2" cellspacing="0"
!Part ID
!Type
!Driving Voltage
!Gain
!Spectral Range (nm)
!Spectral Peak (nm)
!Dark Current (after 30 min)
!Rise Time (ns)
!Transit Time (TT)(ns)
!Transit Time Spread (TTS) (ns)
!Pricing
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r1166.php R1161]
|PMT - Head On
|1000 V
|1,0E+06
|300 to 650
|420
|1-6 nA
|2,5
|27
|2,8
|x
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5509-42.php R5505]
|PMT - Head On
|1750 V
|1,0E+06
|300 to 1400
|900
|10 nA
|3
|23
|1,5
|16 010 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3478.php R3478]
|PMT - Head On
|1700 V
|1,7E+06
|300 to 650
|420
|6 nA
|1,3
|14
|0,36
|3 837 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u-02.php 7400U-02]
|PMT - Head On
|800 V
|5,0E+05
|300 to 850
|500
|2 nA
|0,78
|5,4
|0,23
|6 404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r2083.php R2083]
|PMT - Head On
|3000 V
|2,5E+06
|300 to 650
|420
|100 nA
|0,7
|16
|0,37
|14 955 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u.php 7400-02]
|PMT - Head On
|800 V
|7,0E+05
|300 to 850
|420
|0,2 nA
|0,75
|5,4
|0,28
|6404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3809u-52.php R3809-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|2000/s
|0,15
|0,55
|0,025
|126 346 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5916u-52.php R5916U-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|0,5
|0,18
|1
|0,09
|148 643 SEK
|}
===So whats's up with the MCP's?===
Microchannel Plate PMT, has plates containing numerous small holes, microchannels, which are lined with a secondary emissive dynode material. Electrons are amplified as they drop down the voltage gradients across the microchannel plate.

MCP-PMT shows the fastes time response due to the restricted range of electron paths and short electron travel distance.

Disadvantage is lower gain and photocurrent typ at 100 nA vs. 10-100uA for dyanode PMT
 
[[Image:MCP-PMT.jpg]]

Photomultipliers

2009-02-25T14:17:59Z

St12361:

==Critical Parameters==

{| border="1" cellpadding="5" cellspacing="0"
!Parameter
!Description
!Typical Value (Fast PTM)
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
 

[[Image:PMT_Parameters.jpg]]

==Overview of different PMT's==
{| border="1" cellpadding="2" cellspacing="0"
!Part ID
!Type
!Driving Voltage
!Gain
!Spectral Range (nm)
!Spectral Peak (nm)
!Dark Current (after 30 min)
!Rise Time (ns)
!Transit Time (TT)(ns)
!Transit Time Spread (TTS) (ns)
!Pricing
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r1166.php R1161]
|PMT - Head On
|1000 V
|1,0E+06
|300 to 650
|420
|1-6 nA
|2,5
|27
|2,8
|x
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5509-42.php R5505]
|PMT - Head On
|1750 V
|1,0E+06
|300 to 1400
|900
|10 nA
|3
|23
|1,5
|16 010 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3478.php R3478]
|PMT - Head On
|1700 V
|1,7E+06
|300 to 650
|420
|6 nA
|1,3
|14
|0,36
|3 837 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u-02.php 7400U-02]
|PMT - Head On
|800 V
|5,0E+05
|300 to 850
|500
|2 nA
|0,78
|5,4
|0,23
|6404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r2083.php R2083]
|PMT - Head On
|3000 V
|2,5E+06
|300 to 650
|420
|100 nA
|0,7
|16
|0,37
|14 955 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u.php 7400-02]
|PMT - Head On
|800 V
|7,0E+05
|300 to 850
|420
|0,2 nA
|0,75
|5,4
|0,28
|6404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3809u-52.php R3809-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|2000/s
|0,15
|0,55
|0,025
|126,346 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5916u-52.php R5916U-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|0,5
|0,18
|1
|0,09
|148,643 SEK
|}
===So whats's up with the MCP's?===
Microchannel Plate PMT, has plates containing numerous small holes, microchannels, which are lined with a secondary emissive dynode material. Electrons are amplified as they drop down the voltage gradients across the microchannel plate.

MCP-PMT shows the fastes time response due to the restricted range of electron paths and short electron travel distance.

Disadvantage is lower gain and photocurrent typ at 100 nA vs. 10-100uA for dyanode PMT
 
[[Image:MCP-PMT.jpg]]

Photomultipliers

2009-02-24T14:22:44Z

St12361:

==Critical Parameters==

{| border="1" cellpadding="5" cellspacing="0"
!Parameter
!Description
!Typical Value (Fast PTM)
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
 

[[Image:PMT_Parameters.jpg]]

==Overview of different PMT's==
{| border="1" cellpadding="2" cellspacing="0"
!Part ID
!Type
!Driving Voltage
!Gain
!Spectral Range (nm)
!Spectral Peak (nm)
!Dark Current (after 30 min)
!Rise Time (ns)
!Transit Time (TT)(ns)
!Transit Time Spread (TTS) (ns)
!Pricing
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r1166.php R1161]
|PMT - Head On
|1000 V
|1,0E+06
|300 to 650
|420
|1-6 nA
|2,5
|27
|2,8
|x
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5509-42.php R5505]
|PMT - Head On
|1750 V
|1,0E+06
|300 to 1400
|900
|10 nA
|3
|23
|1,5
|x
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3478.php R3478]
|PMT - Head On
|1700 V
|1,7E+06
|300 to 650
|420
|6 nA
|1,3
|14
|0,36
|x
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u-02.php 7400U-02]
|PMT - Head On
|800 V
|5,0E+05
|300 to 850
|500
|2 nA
|0,78
|5,4
|0,23
|6404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r7400u.php 7400-02]
|PMT - Head On
|800 V
|7,0E+05
|300 to 850
|420
|0,2 nA
|0,75
|5,4
|0,28
|6404 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r3809u-52.php R3809-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|2000/s
|0,15
|0,55
|0,025
|126,346 SEK
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r5916u-52.php R5916U-52]
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|0,5
|0,18
|1
|0,09
|148,643 SEK
|}
===So whats's up with the MCP's?===
Microchannel Plate PMT, has plates containing numerous small holes, microchannels, which are lined with a secondary emissive dynode material. Electrons are amplified as they drop down the voltage gradients across the microchannel plate.

MCP-PMT shows the fastes time response due to the restricted range of electron paths and short electron travel distance.

Disadvantage is lower gain and photocurrent typ at 100 nA vs. 10-100uA for dyanode PMT
 
[[Image:MCP-PMT.jpg]]

Photomultipliers

2009-02-24T14:19:03Z

St12361:

==Critical Parameters==

{| border="1" cellpadding="5" cellspacing="0"
!Parameter
!Description
!Typical Value (Fast PTM)
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
 
 
[[Image:PMT_Parameters.jpg]]

==Overview of different PMT's==
{| border="1" cellpadding="2" cellspacing="0"
!Part ID
!Type
!Driving Voltage
!Gain
!Spectral Range (nm)
!Spectral Peak (nm)
!Dark Current (after 30 min)
!Rise Time (ns)
!Transit Time (TT)(ns)
!Transit Time Spread (TTS) (ns)
!Pricing
|-
|[http://sales.hamamatsu.com/en/products/electron-tube-division/detectors/photomultiplier-tubes/part-r1166.php R1161]
|PMT - Head On
|1000 V
|1,0E+06
|300 to 650
|420
|1-6 nA
|2,5
|27
|2,8
|x
|-
|R5505
|PMT - Head On
|1750 V
|1,0E+06
|300 to 1400
|900
|10 nA
|3
|23
|1,5
|x
|-
|R3478
|PMT - Head On
|1700 V
|1,7E+06
|300 to 650
|420
|6 nA
|1,3
|14
|0,36
|x
|-
|7400U-02
|PMT - Head On
|800 V
|5,0E+05
|300 to 850
|500
|2 nA
|0,78
|5,4
|0,23
|6404 SEK
|-
|7400-02
|PMT - Head On
|800 V
|7,0E+05
|300 to 850
|420
|0,2 nA
|0,75
|5,4
|0,28
|6404 SEK
|-
|R380952
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|2000/s
|0,15
|0,55
|0,025
|126,346 SEK
|-
|R5916U-52
|MCP - PMT
|3000 V
|2,0E+05
|160 to 650
|400
|0,5
|0,18
|1
|0,09
|148,643 SEK
|}
===So whats's up with the MCP's?===
Microchannel Plate PMT, has plates containing numerous small holes, microchannels, which are lined with a secondary emissive dynode material. Electrons are amplified as they drop down the voltage gradients across the microchannel plate.

MCP-PMT shows the fastes time response due to the restricted range of electron paths and short electron travel distance.

Disadvantage is lower gain and photocurrent typ at 100 nA vs. 10-100uA for dyanode PMT
 
[[Image:MCP-PMT.jpg]]

File:MCP-PMT.jpg

2009-02-24T13:46:43Z

St12361:

Photomultipliers

2009-02-24T13:45:15Z

St12361:

Photomultipliers

2009-02-24T13:43:07Z

St12361:

Photomultipliers

2009-02-24T13:29:20Z

St12361:

Photomultipliers

2009-02-24T13:12:36Z

St12361:

===Critical Parameters===

{| border="1" cellpadding="5" cellspacing="0"
|Parameter
|Description
|Typical Value (Fast PTM)
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
[[Image:PMT_Parameters.jpg]]

Photomultipliers

2009-02-24T13:11:13Z

St12361:

Photomultipliers

2009-02-24T13:10:28Z

St12361:

File:PMT Parameters.jpg

2009-02-24T13:09:38Z

St12361:

Photomultipliers

2009-02-24T13:08:28Z

St12361:

Photomultipliers

2009-02-24T12:55:12Z

St12361: New page: <big>'''Photomultipliers'''</big> ===Critical Parameters=== {| border="1" cellpadding="5" cellspacing="0" |Parameter |Description |Typical Value (Fast PTM) |- |Rise Time (TR) |The time ...

<big>'''Photomultipliers'''</big>

===Critical Parameters===

{| border="1" cellpadding="5" cellspacing="0"
|Parameter
|Description
|Typical Value (Fast PTM)
|-
|Rise Time (TR)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|0,05 (MCP) to 3 ns
|-
|Transit Time (TT)
|The time interval between the arrival of photon at the cathode and the arrival of the amplified pulse at the anode
|MCP:0,5 ns. PMT: 5-30 ns
|-
|Transit Time Spread (TTS)
|Considered as the most important specification for time-resolved measurements; the timing variation due to the different geometric paths that the electrons can take from the cathode to the anode
|MCP: 0,025 ns. PMT: 0,2-1,5 ns
|}
[[Image:[[Image:PMT_Parameters.jpg]]]]

PET Project

2009-02-24T12:23:11Z

St12361: