ift - User contributions [en]

Busy Box and related

2009-12-18T14:13:40Z

St09909: /* Related documents for BusyBox */

== Overview ==
[[Image:Block_busybox.jpg‎|thumb|791px|center|Block diagram BusyBox]]
 
ALICE is one of four large detectors situated at the collision points in the Large Hadron Collider (LHC) at CERN. The BusyBox is used by four of ALICE’s sub-detectors: Time Projection Chamber (TPC), Photon Spectrometer (PHOS), Forward Multiplicity Detector (FMD) and Electromagnetic Calorimeter (EMCal)

Triggers initiate data readout from ALICE’s sub-detectors and are received by the DCS board via an optical cable interface. The triggers and associated data are routed from the TTCrx ASIC on the DCS board to the BusyBox FPGA(s). Here, the L1a and Serial B line raw data is decoded by the Trigger Receiver firmware module.

Every time a trigger sequence starts the Fee starts buffering data, i.e. a buffer in the Fee is used. A valid trigger sequence ends with an L2a trigger and the event data along with the event ID is sent to the D-RORCs.

The purpose of BusyBox is to let the Central Trigger Processor (CTP) know when the Fee’s buffers are full by asserting a busy signal which prevents further issuing of triggers. The BusyBox and D-RORCs receives a unique event ID from the Fee after an event. After a valid trigger sequence ends the BusyBox will ask the D-RORCs if they have received the same event ID as the BusyBox did. If they do not reply with the same ID it means data has not been shipped from the Fee to the D-RORC, hence, the buffer in the Fee still holds event data.

The Fee buffers can hold 4 or 8 events and the BusyBox keeps track of free buffers. The busy is asserted if the buffers are full.

Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.

The BusyBoxes are located in the DAQ counting rom.

== BusyBox Hardware tests at UiB ==
In one of our labs at UiB we have a setup for testing new BusyBox firmware in hardware before releasing it. The setup features a full readout chain for one channel of the ALICE TPC. 
===== Components in LAB setup : =====
* Local Trigger Crate (LTU)
* Readout Control Unit (RCU) with Front End Cards (FEC)
* Local Data Concentrator (LDC) with 3 DAQ ReadOut Receiver Cards (DRORC) and date software.
* BusyBox with 2 FPGAs but only 1U rack.

See Also [[How to run the RCU - DRORC - Busybox setup]]

== BusyBox Firmware ==

See [[Busy_Box_and_related/BusyBox Registers|BusyBox Registers]] for latest updated information on firmware registers.

==== Source Code Repositories ====

*[http://svn.ift.uib.no/svn/busybox_firmware BusyBox SVN repository]
*[http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/vhdlcvs/trigger_receiver/ Trigger Receiver CVS]

====BusyBox FPGAs====

There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. Alternatively fpga2 can be prgrammed with 'dummy.bit'.

==== Compiled BusyBox Firmware Versions ====

=====Revision 31=====
;:* Using Trigger Receiver Module v.1.3
;:* Now handles orphan L2 Accept triggers by looking at the payload bit in the event info.
;:;Download
;::*[http://web.ift.uib.no/~st09909/BusyBox/revision31/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]
;::*[http://web.ift.uib.no/~st09909/BusyBox/revision31/busybox_fpga1.bit busybox_fpga1.bit]
;::*[http://web.ift.uib.no/~st09909/BusyBox/revision31/busybox_fpga2.bit busybox_fpga2.bit]

======Versioning======
The busybox version number is now the same as the revision number of the source in SVN it was generated from. This should make it possible to get the original source files for any programming file.
A register for the version number exists in the ctrl_regs module.

=====Revision 41=====
======Non functional FW changes======
# Signal names used globally in the design have been renamed: clocka => clk200, clockb => clk40, areset => rst40 /rst200
# All processes in all VHDL files used in the design, except for the trigger receiver module, have been updated to implement a synchronous reset.
# Since a stable clock is required for to perform a proper synchronous reset, a new module that implements reset logic has been added to the design in busylogic_top module. The reset logic will assert reset for as long as the DCM has not locked on the incoming clock. The reset will be released synchronously about 10 cycles after the DCM has asserted its locked signal.
# Since the actual clock of the LHC is 40.08 MHz and not the nominal 40 MHz the constraints for the implementation tools has been set 41 MHz. (85 degrees celsius, 41 MHz, 1.14 V)

======Event verification module (event_validator_top)======
This module has been modified so that the event ID queue now also contains the event info and event errors in addition to the event ID. The event info and event errors for the newest and current events are made available as registers. This extra info about the trigger sequence can be helpful when debugging.
The event info contains the payload bit which is forwarded to the busy_controller. It is used in the process of calculating used MEBs.

======Serial decoder======
The serial decoder has been changed to reduce the resource usage. This module is replicated many times in the design so any improvement is significant. The old architecture used a shift register long enough to hold all bit-samples for one data frame (about 100 samples). The frame was captured in one go when a valid capture condition was found in the samples. The new architecture uses shorter shift register (about 10 samples) and only looks at a few samples at a time. Once the start condition is found it will capture the bits of the frame sequentially, bit by bit.
The new architecture of this module has led to great improvements in resource usage. BusyBox firmware with 96 channels used to occupy approximately 96% of the FPGA. This number has been reduced to approximately 66%. Reduced resource usage makes it easier for the implementation tools to generate the programming file and it should also reduce the TDP of the device under operation.

======DCS arbiter and address decoder======
The architecture of this module has been updated to make it more readable and to register inputs such as address and data from the DCS bus master.

======Registers======
Extra registers has been added and an updated register table exists on the wiki : [[Busy_Box_and_related/BusyBox_Registers|BusyBox Registers]]
In short:
#Number of implemented channels. This number is actually the same as the generic g_num_channels.
#Current Trigger Event Info
#Current Trigger Event Error
#Newest Trigger Event Info
#Newest Trigger Event Error

======Download======
*[http://web.ift.uib.no/~st09909/BusyBox/BusyBoxUserGuide.pdf BusyBoxUserGuide.pdf]
*[http://web.ift.uib.no/~st09909/BusyBox/revision41/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]
*[http://web.ift.uib.no/~st09909/BusyBox/revision41/busybox_fpga1.bit busybox_fpga1.bit]
*[http://web.ift.uib.no/~st09909/BusyBox/revision41/busybox_fpga2.bit busybox_fpga2.bit]

==== DCS board firmware for BusyBox ====

The DCS board in the BusyBox uses special firmware. See
[[Electronics for the Time Projection Chamber (TPC)#Download_Section|Electronics for the TPC]]

====Generating FPGA configuration files from source code====

# Check out the desired revision from the SVN repository.
# Navigate to .../busybox_firmware/trunk/ISE_projects
# Run the TCL script named bbiseproject.tcl with Xilinx' TCL interpreter. The script takes three commandline arguments : 
#*<tt>fpga_version</tt> - see [[#BusyBox FPGAs]]
#*<tt>source_dir</tt> - where the source code is located. Including constraints and cores.
#*<tt>project_dir</tt> - location where project is created. Note folder has to exist and should not already contain an ISE project.
#:Example: <code>D:\busybox_firmware\trunk\ISE_projects>xtclsh bbiseproject.tcl busybox_fpga1_solo ..\source test </code>
#Generate the cores with CoreGen (If it not already done)
#:This can be done by using the CoreGen GUI or by invoking coregen in batch mode from the commandline. To use the GUI; start coregen while in <tt>.../busybox_firmware/trunk/source/cores</tt>.
#: For batch mode : <tt>.../busybox_firmware/trunk/source/cores/coregen -b 'core'.xco</tt> replace 'core' with real name for all *.xco-files.
#: Example with DOS for loop: <tt>D:\busybox_firmware\trunk\source\cores>FOR %i IN (*.xco) DO coregen -b %i</tt>
#Open the project with ISE Project Navigator.
#Run process 'Generate Programming File'
 

== Related documents for BusyBox ==
#[http://web.ift.uib.no/~st09909/BusyBox/BusyBoxUserGuide.pdf BusyBox User Guide (updated for FW rev 41)]

#[[Media:Rikard_Bolgen_-_BusyBox_User_Guide.pdf‎|Master Thesis, Rikard Bølgen]]
#[[Electronics_for_the_Time_Projection_Chamber_%28TPC%29#RCU_Trigger_Receiver_Module|RCU Trigger Receiver Module]]
#[[Media:master_thesis_magne_munkejord.pdf|Master Thesis, Magne Munkejord]]
#[[Media:jalme_phd-thesis.pdf|PhD Thesis, Johan Alme]]
#[http://folk.uib.no/st09909/HIB_selectMAP_rapport/Sluttrapport/SelectMAP_Kernel_Module_-_Sluttrapport.pdf SelectMAP driver (Report be HIB students, in norwegian)]
#[http://web.ift.uib.no/~st09909/BusyBox/BusyBoxFeeServer.pdf BusyBox FeeServer]

[[Category:Alice]]
[[Category:Trigger]]

Busy Box and related

2009-12-18T10:47:03Z

St09909: /* Compiled BusyBox Firmware Versions */

== Overview ==
[[Image:Block_busybox.jpg‎|thumb|791px|center|Block diagram BusyBox]]
 
ALICE is one of four large detectors situated at the collision points in the Large Hadron Collider (LHC) at CERN. The BusyBox is used by four of ALICE’s sub-detectors: Time Projection Chamber (TPC), Photon Spectrometer (PHOS), Forward Multiplicity Detector (FMD) and Electromagnetic Calorimeter (EMCal)

Triggers initiate data readout from ALICE’s sub-detectors and are received by the DCS board via an optical cable interface. The triggers and associated data are routed from the TTCrx ASIC on the DCS board to the BusyBox FPGA(s). Here, the L1a and Serial B line raw data is decoded by the Trigger Receiver firmware module.

Every time a trigger sequence starts the Fee starts buffering data, i.e. a buffer in the Fee is used. A valid trigger sequence ends with an L2a trigger and the event data along with the event ID is sent to the D-RORCs.

The purpose of BusyBox is to let the Central Trigger Processor (CTP) know when the Fee’s buffers are full by asserting a busy signal which prevents further issuing of triggers. The BusyBox and D-RORCs receives a unique event ID from the Fee after an event. After a valid trigger sequence ends the BusyBox will ask the D-RORCs if they have received the same event ID as the BusyBox did. If they do not reply with the same ID it means data has not been shipped from the Fee to the D-RORC, hence, the buffer in the Fee still holds event data.

The Fee buffers can hold 4 or 8 events and the BusyBox keeps track of free buffers. The busy is asserted if the buffers are full.

Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.

The BusyBoxes are located in the DAQ counting rom.

== BusyBox Hardware tests at UiB ==
In one of our labs at UiB we have a setup for testing new BusyBox firmware in hardware before releasing it. The setup features a full readout chain for one channel of the ALICE TPC. 
===== Components in LAB setup : =====
* Local Trigger Crate (LTU)
* Readout Control Unit (RCU) with Front End Cards (FEC)
* Local Data Concentrator (LDC) with 3 DAQ ReadOut Receiver Cards (DRORC) and date software.
* BusyBox with 2 FPGAs but only 1U rack.

See Also [[How to run the RCU - DRORC - Busybox setup]]

== BusyBox Firmware ==

See [[Busy_Box_and_related/BusyBox Registers|BusyBox Registers]] for latest updated information on firmware registers.

==== Source Code Repositories ====

*[http://svn.ift.uib.no/svn/busybox_firmware BusyBox SVN repository]
*[http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/vhdlcvs/trigger_receiver/ Trigger Receiver CVS]

====BusyBox FPGAs====

There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. Alternatively fpga2 can be prgrammed with 'dummy.bit'.

==== Compiled BusyBox Firmware Versions ====

=====Revision 31=====
;:* Using Trigger Receiver Module v.1.3
;:* Now handles orphan L2 Accept triggers by looking at the payload bit in the event info.
;:;Download
;::*[http://web.ift.uib.no/~st09909/BusyBox/revision31/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]
;::*[http://web.ift.uib.no/~st09909/BusyBox/revision31/busybox_fpga1.bit busybox_fpga1.bit]
;::*[http://web.ift.uib.no/~st09909/BusyBox/revision31/busybox_fpga2.bit busybox_fpga2.bit]

======Versioning======
The busybox version number is now the same as the revision number of the source in SVN it was generated from. This should make it possible to get the original source files for any programming file.
A register for the version number exists in the ctrl_regs module.

=====Revision 41=====
======Non functional FW changes======
# Signal names used globally in the design have been renamed: clocka => clk200, clockb => clk40, areset => rst40 /rst200
# All processes in all VHDL files used in the design, except for the trigger receiver module, have been updated to implement a synchronous reset.
# Since a stable clock is required for to perform a proper synchronous reset, a new module that implements reset logic has been added to the design in busylogic_top module. The reset logic will assert reset for as long as the DCM has not locked on the incoming clock. The reset will be released synchronously about 10 cycles after the DCM has asserted its locked signal.
# Since the actual clock of the LHC is 40.08 MHz and not the nominal 40 MHz the constraints for the implementation tools has been set 41 MHz. (85 degrees celsius, 41 MHz, 1.14 V)

======Event verification module (event_validator_top)======
This module has been modified so that the event ID queue now also contains the event info and event errors in addition to the event ID. The event info and event errors for the newest and current events are made available as registers. This extra info about the trigger sequence can be helpful when debugging.
The event info contains the payload bit which is forwarded to the busy_controller. It is used in the process of calculating used MEBs.

======Serial decoder======
The serial decoder has been changed to reduce the resource usage. This module is replicated many times in the design so any improvement is significant. The old architecture used a shift register long enough to hold all bit-samples for one data frame (about 100 samples). The frame was captured in one go when a valid capture condition was found in the samples. The new architecture uses shorter shift register (about 10 samples) and only looks at a few samples at a time. Once the start condition is found it will capture the bits of the frame sequentially, bit by bit.
The new architecture of this module has led to great improvements in resource usage. BusyBox firmware with 96 channels used to occupy approximately 96% of the FPGA. This number has been reduced to approximately 66%. Reduced resource usage makes it easier for the implementation tools to generate the programming file and it should also reduce the TDP of the device under operation.

======DCS arbiter and address decoder======
The architecture of this module has been updated to make it more readable and to register inputs such as address and data from the DCS bus master.

======Registers======
Extra registers has been added and an updated register table exists on the wiki : [[Busy_Box_and_related/BusyBox_Registers|BusyBox Registers]]
In short:
#Number of implemented channels. This number is actually the same as the generic g_num_channels.
#Current Trigger Event Info
#Current Trigger Event Error
#Newest Trigger Event Info
#Newest Trigger Event Error

======Download======
*[http://web.ift.uib.no/~st09909/BusyBox/BusyBoxUserGuide.pdf BusyBoxUserGuide.pdf]
*[http://web.ift.uib.no/~st09909/BusyBox/revision41/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]
*[http://web.ift.uib.no/~st09909/BusyBox/revision41/busybox_fpga1.bit busybox_fpga1.bit]
*[http://web.ift.uib.no/~st09909/BusyBox/revision41/busybox_fpga2.bit busybox_fpga2.bit]

==== DCS board firmware for BusyBox ====

The DCS board in the BusyBox uses special firmware. See
[[Electronics for the Time Projection Chamber (TPC)#Download_Section|Electronics for the TPC]]

====Generating FPGA configuration files from source code====

# Check out the desired revision from the SVN repository.
# Navigate to .../busybox_firmware/trunk/ISE_projects
# Run the TCL script named bbiseproject.tcl with Xilinx' TCL interpreter. The script takes three commandline arguments : 
#*<tt>fpga_version</tt> - see [[#BusyBox FPGAs]]
#*<tt>source_dir</tt> - where the source code is located. Including constraints and cores.
#*<tt>project_dir</tt> - location where project is created. Note folder has to exist and should not already contain an ISE project.
#:Example: <code>D:\busybox_firmware\trunk\ISE_projects>xtclsh bbiseproject.tcl busybox_fpga1_solo ..\source test </code>
#Generate the cores with CoreGen (If it not already done)
#:This can be done by using the CoreGen GUI or by invoking coregen in batch mode from the commandline. To use the GUI; start coregen while in <tt>.../busybox_firmware/trunk/source/cores</tt>.
#: For batch mode : <tt>.../busybox_firmware/trunk/source/cores/coregen -b 'core'.xco</tt> replace 'core' with real name for all *.xco-files.
#: Example with DOS for loop: <tt>D:\busybox_firmware\trunk\source\cores>FOR %i IN (*.xco) DO coregen -b %i</tt>
#Open the project with ISE Project Navigator.
#Run process 'Generate Programming File'
 

== Related documents for BusyBox ==
#[[Media:Rikard_Bolgen_-_BusyBox_User_Guide.pdf|Busybox User Guide, Rikard Bølgen]]
#[[Media:Rikard_Bolgen_-_BusyBox_User_Guide.pdf‎|Master Thesis, Rikard Bølgen]]
#[[Electronics_for_the_Time_Projection_Chamber_%28TPC%29#RCU_Trigger_Receiver_Module|RCU Trigger Receiver Module]]
#[[Media:master_thesis_magne_munkejord.pdf|Master Thesis, Magne Munkejord]]
#[[Media:jalme_phd-thesis.pdf|PhD Thesis, Johan Alme]]
#[http://folk.uib.no/st09909/HIB_selectMAP_rapport/Sluttrapport/SelectMAP_Kernel_Module_-_Sluttrapport.pdf SelectMAP driver (Report be HIB students, in norwegian)]

[[Category:Alice]]
[[Category:Trigger]]

Busy Box and related

2009-12-18T10:42:36Z

St09909: /* Revision 41 */

== Overview ==
[[Image:Block_busybox.jpg‎|thumb|791px|center|Block diagram BusyBox]]
 
ALICE is one of four large detectors situated at the collision points in the Large Hadron Collider (LHC) at CERN. The BusyBox is used by four of ALICE’s sub-detectors: Time Projection Chamber (TPC), Photon Spectrometer (PHOS), Forward Multiplicity Detector (FMD) and Electromagnetic Calorimeter (EMCal)

Triggers initiate data readout from ALICE’s sub-detectors and are received by the DCS board via an optical cable interface. The triggers and associated data are routed from the TTCrx ASIC on the DCS board to the BusyBox FPGA(s). Here, the L1a and Serial B line raw data is decoded by the Trigger Receiver firmware module.

Every time a trigger sequence starts the Fee starts buffering data, i.e. a buffer in the Fee is used. A valid trigger sequence ends with an L2a trigger and the event data along with the event ID is sent to the D-RORCs.

The purpose of BusyBox is to let the Central Trigger Processor (CTP) know when the Fee’s buffers are full by asserting a busy signal which prevents further issuing of triggers. The BusyBox and D-RORCs receives a unique event ID from the Fee after an event. After a valid trigger sequence ends the BusyBox will ask the D-RORCs if they have received the same event ID as the BusyBox did. If they do not reply with the same ID it means data has not been shipped from the Fee to the D-RORC, hence, the buffer in the Fee still holds event data.

The Fee buffers can hold 4 or 8 events and the BusyBox keeps track of free buffers. The busy is asserted if the buffers are full.

Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.

The BusyBoxes are located in the DAQ counting rom.

== BusyBox Hardware tests at UiB ==
In one of our labs at UiB we have a setup for testing new BusyBox firmware in hardware before releasing it. The setup features a full readout chain for one channel of the ALICE TPC. 
===== Components in LAB setup : =====
* Local Trigger Crate (LTU)
* Readout Control Unit (RCU) with Front End Cards (FEC)
* Local Data Concentrator (LDC) with 3 DAQ ReadOut Receiver Cards (DRORC) and date software.
* BusyBox with 2 FPGAs but only 1U rack.

See Also [[How to run the RCU - DRORC - Busybox setup]]

== BusyBox Firmware ==

See [[Busy_Box_and_related/BusyBox Registers|BusyBox Registers]] for latest updated information on firmware registers.

==== Source Code Repositories ====

*[http://svn.ift.uib.no/svn/busybox_firmware BusyBox SVN repository]
*[http://web.ift.uib.no/kjekscgi-bin/viewcvs.cgi/vhdlcvs/trigger_receiver/ Trigger Receiver CVS]

====BusyBox FPGAs====

There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. Alternatively fpga2 can be prgrammed with 'dummy.bit'.

==== Compiled BusyBox Firmware Versions ====

=====Revision 31=====
;:* Using Trigger Receiver Module v.1.3
;:* Now handles orphan L2 Accept triggers by looking at the payload bit in the event info.
;:;Download
;::*[http://folk.uib.no/st09909/revision31/busybox_fpga1_solo.bit busybox_fpga1_solo.bit]
;::*[http://folk.uib.no/st09909/revision31/busybox_fpga1.bit busybox_fpga1.bit]
;::*[http://folk.uib.no/st09909/revision31/busybox_fpga2.bit busybox_fpga2.bit]

======Versioning======
The busybox version number is now the same as the revision number of the source in SVN it was generated from. This should make it possible to get the original source files for any programming file.
A register for the version number exists in the ctrl_regs module.



=====Revision 41=====
======Non functional FW changes======
# Signal names used globally in the design have been renamed: clocka => clk200, clockb => clk40, areset => rst40 /rst200
# All processes in all VHDL files used in the design, except for the trigger receiver module, have been updated to implement a synchronous reset.
# Since a stable clock is required for to perform a proper synchronous reset, a new module that implements reset logic has been added to the design in busylogic_top module. The reset logic will assert reset for as long as the DCM has not locked on the incoming clock. The reset will be released synchronously about 10 cycles after the DCM has asserted its locked signal.
# Since the actual clock of the LHC is 40.08 MHz and not the nominal 40 MHz the constraints for the implementation tools has been set 41 MHz. (85 degrees celsius, 41 MHz, 1.14 V)

======Event verification module (event_validator_top)======
This module has been modified so that the event ID queue now also contains the event info and event errors in addition to the event ID. The event info and event errors for the newest and current events are made available as registers. This extra info about the trigger sequence can be helpful when debugging.
The event info contains the payload bit which is forwarded to the busy_controller. It is used in the process of calculating used MEBs.

======Serial decoder======
The serial decoder has been changed to reduce the resource usage. This module is replicated many times in the design so any improvement is significant. The old architecture used a shift register long enough to hold all bit-samples for one data frame (about 100 samples). The frame was captured in one go when a valid capture condition was found in the samples. The new architecture uses shorter shift register (about 10 samples) and only looks at a few samples at a time. Once the start condition is found it will capture the bits of the frame sequentially, bit by bit.
The new architecture of this module has led to great improvements in resource usage. BusyBox firmware with 96 channels used to occupy approximately 96% of the FPGA. This number has been reduced to approximately 66%. Reduced resource usage makes it easier for the implementation tools to generate the programming file and it should also reduce the TDP of the device under operation.

======DCS arbiter and address decoder======
The architecture of this module has been updated to make it more readable and to register inputs such as address and data from the DCS bus master.

======Registers======
Extra registers has been added and an updated register table exists on the wiki : [[Busy_Box_and_related/BusyBox_Registers|BusyBox Registers]]
In short:
#Number of implemented channels. This number is actually the same as the generic g_num_channels.
#Current Trigger Event Info
#Current Trigger Event Error
#Newest Trigger Event Info
#Newest Trigger Event Error

======Download======

==== DCS board firmware for BusyBox ====

The DCS board in the BusyBox uses special firmware. See
[[Electronics for the Time Projection Chamber (TPC)#Download_Section|Electronics for the TPC]]

====Generating FPGA configuration files from source code====

# Check out the desired revision from the SVN repository.
# Navigate to .../busybox_firmware/trunk/ISE_projects
# Run the TCL script named bbiseproject.tcl with Xilinx' TCL interpreter. The script takes three commandline arguments : 
#*<tt>fpga_version</tt> - see [[#BusyBox FPGAs]]
#*<tt>source_dir</tt> - where the source code is located. Including constraints and cores.
#*<tt>project_dir</tt> - location where project is created. Note folder has to exist and should not already contain an ISE project.
#:Example: <code>D:\busybox_firmware\trunk\ISE_projects>xtclsh bbiseproject.tcl busybox_fpga1_solo ..\source test </code>
#Generate the cores with CoreGen (If it not already done)
#:This can be done by using the CoreGen GUI or by invoking coregen in batch mode from the commandline. To use the GUI; start coregen while in <tt>.../busybox_firmware/trunk/source/cores</tt>.
#: For batch mode : <tt>.../busybox_firmware/trunk/source/cores/coregen -b 'core'.xco</tt> replace 'core' with real name for all *.xco-files.
#: Example with DOS for loop: <tt>D:\busybox_firmware\trunk\source\cores>FOR %i IN (*.xco) DO coregen -b %i</tt>
#Open the project with ISE Project Navigator.
#Run process 'Generate Programming File'
 

== Related documents for BusyBox ==
#[[Media:Rikard_Bolgen_-_BusyBox_User_Guide.pdf|Busybox User Guide, Rikard Bølgen]]
#[[Media:Rikard_Bolgen_-_BusyBox_User_Guide.pdf‎|Master Thesis, Rikard Bølgen]]
#[[Electronics_for_the_Time_Projection_Chamber_%28TPC%29#RCU_Trigger_Receiver_Module|RCU Trigger Receiver Module]]
#[[Media:master_thesis_magne_munkejord.pdf|Master Thesis, Magne Munkejord]]
#[[Media:jalme_phd-thesis.pdf|PhD Thesis, Johan Alme]]
#[http://folk.uib.no/st09909/HIB_selectMAP_rapport/Sluttrapport/SelectMAP_Kernel_Module_-_Sluttrapport.pdf SelectMAP driver (Report be HIB students, in norwegian)]

[[Category:Alice]]
[[Category:Trigger]]

Busy Box and related

2009-12-14T15:47:22Z

St09909: /* Related documents for BusyBox */

Busy Box and related/BusyBox Registers

2009-11-25T15:25:58Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - 0x0 & RequestID(3:0) & OrbitID(23:16)
* Address ending "01" - OrbitID(15:0)
* Address ending "10" - 0x0 BunchCountID(11:0)
* Address ending "11" - DRORCID(7:0) & ChannelNumber(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 40
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Current Trigger Event Info(12:0)
|0x2050
|R
|Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(24:16)
|0x2051
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(15:0)
|0x2052
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Newest Trigger Event Info(12:0)
|0x2054
|R
|Holds the Event Info for newest eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Newest Trigger Event Error(24:16)
|0x2055
|R
|Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Newest Trigger Event Error(15:0)
|0x2056
|R
|Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="90"|Bit slice
!Description
|----
|rowspan="11"|Control
|rowspan="11"|0x3000
|RW
|[15:13]
|Unused
|----
|RW
|[12]
|Trigger Input Mask Enable. Default=0
|----
|RW
|[11]
|L1a message mask. Default=1
|----
|RW
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|RW
|[9]
|L2r FIFO storage mask. Default=1
|----
|RW
|[8]
|L2a FIFO storage mask. Default=1
|----
|RW
|[7:4]
|Unused
|----
|RW
|[3]
|L0 support. Default=1
|----
|RW
|[2]
|Enable RoI decoding. Default=0
|----
|RW
|[1]
|Disable_error_masking. Default=0
|----
|RW
|[0]
|Serial B channel on/off. Default=1
|----
|rowspan="6"|Control
|rowspan="6"|0x3001
|R
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|R
|[7:4]
|CDH version. Default=0x2
|----
|R
|[3]
|Not Used
|----
|R
|[2]
|Busy (receiving sequence) -
|----
|R
|[1]
|Run Active -
|----
|R
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|rowspan="2"|L1_Latency
|rowspan="2"|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info
|0x3051
|R
|[12:0]
|Latest Received Event information:
|----
|colspan="2" rowspan="10"|
|R
|[12]
|Include payload
|----
|R
|[11]
|Event has L2 Accept trigger
|----
|R
|[10]
|Event has L2 Reject trigger
|----
|R
|[9]
|Calibration trigger event
|----
|R
|[8]
|Software trigger event
|----
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|R
|[3]
|NA(=‘0’)
|----
|R
|[2]
|NA(=‘0’)
|----
|R
|[1]
|Region of Interest announced (=ESR)
|----
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x3053
|R
|[15:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="16"|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|R
|[14]
|Missing L1
|----
|R
|[13]
|Boundary L1
|----
|R
|[12]
|Spurious L1
|----
|R
|[11]
|Missing L0
|----
|R
|[10]
|Spurious L0
|----
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|Incomplete L2a Message
|----
|R
|[6]
|Incomplete L1 Message
|----
|R
|[5]
|Unknown Message Address Received
|----
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x3054
|R
|[8:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="9"|
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|L2 message content error
|----
|R
|[6]
|L1 message content error
|----
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|R
|[4]
|NA (= ‘0’)
|----
|R
|[3]
|NA (= ‘0’)
|----
|R
|[2]
|L2 message missing/timeout
|----
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related/BusyBox Registers

2009-11-25T15:24:54Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - 0x0 & RequestID(3:0) & OrbitID(23:16)
* Address ending "01" - OrbitID(15:0)
* Address ending "10" - 0x0 BunchCountID(11:0)
* Address ending "11" - DRORCID(7:0) & ChannelNumber(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Current Trigger Event Info(12:0)
|0x2050
|R
|Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(24:16)
|0x2051
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(15:0)
|0x2052
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Newest Trigger Event Info(12:0)
|0x2054
|R
|Holds the Event Info for newest eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Newest Trigger Event Error(24:16)
|0x2055
|R
|Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Newest Trigger Event Error(15:0)
|0x2056
|R
|Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="90"|Bit slice
!Description
|----
|rowspan="11"|Control
|rowspan="11"|0x3000
|RW
|[15:13]
|Unused
|----
|RW
|[12]
|Trigger Input Mask Enable. Default=0
|----
|RW
|[11]
|L1a message mask. Default=1
|----
|RW
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|RW
|[9]
|L2r FIFO storage mask. Default=1
|----
|RW
|[8]
|L2a FIFO storage mask. Default=1
|----
|RW
|[7:4]
|Unused
|----
|RW
|[3]
|L0 support. Default=1
|----
|RW
|[2]
|Enable RoI decoding. Default=0
|----
|RW
|[1]
|Disable_error_masking. Default=0
|----
|RW
|[0]
|Serial B channel on/off. Default=1
|----
|rowspan="6"|Control
|rowspan="6"|0x3001
|R
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|R
|[7:4]
|CDH version. Default=0x2
|----
|R
|[3]
|Not Used
|----
|R
|[2]
|Busy (receiving sequence) -
|----
|R
|[1]
|Run Active -
|----
|R
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|rowspan="2"|L1_Latency
|rowspan="2"|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info
|0x3051
|R
|[12:0]
|Latest Received Event information:
|----
|colspan="2" rowspan="10"|
|R
|[12]
|Include payload
|----
|R
|[11]
|Event has L2 Accept trigger
|----
|R
|[10]
|Event has L2 Reject trigger
|----
|R
|[9]
|Calibration trigger event
|----
|R
|[8]
|Software trigger event
|----
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|R
|[3]
|NA(=‘0’)
|----
|R
|[2]
|NA(=‘0’)
|----
|R
|[1]
|Region of Interest announced (=ESR)
|----
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x3053
|R
|[15:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="16"|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|R
|[14]
|Missing L1
|----
|R
|[13]
|Boundary L1
|----
|R
|[12]
|Spurious L1
|----
|R
|[11]
|Missing L0
|----
|R
|[10]
|Spurious L0
|----
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|Incomplete L2a Message
|----
|R
|[6]
|Incomplete L1 Message
|----
|R
|[5]
|Unknown Message Address Received
|----
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x3054
|R
|[8:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="9"|
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|L2 message content error
|----
|R
|[6]
|L1 message content error
|----
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|R
|[4]
|NA (= ‘0’)
|----
|R
|[3]
|NA (= ‘0’)
|----
|R
|[2]
|L2 message missing/timeout
|----
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related/BusyBox Registers

2009-11-25T15:22:52Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - 0x0 & RequestID(3:0) & OrbitID(23:16)
* Address ending "01" - OrbitID(15:0)
* Address ending "10" - 0x0 BunchCountID(11:0)
* Address ending "11" - DRORCID(7:0) & ChannelNumber(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Current Trigger Event Info(12:0)
|0x2050
|R
|Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(24:16)
|0x2051
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(15:0)
|0x2052
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Info(12:0)
|0x2054
|R
|Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(24:16)
|0x2055
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Current Trigger Event Error(15:0)
|0x2056
|R
|Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="90"|Bit slice
!Description
|----
|rowspan="11"|Control
|rowspan="11"|0x3000
|RW
|[15:13]
|Unused
|----
|RW
|[12]
|Trigger Input Mask Enable. Default=0
|----
|RW
|[11]
|L1a message mask. Default=1
|----
|RW
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|RW
|[9]
|L2r FIFO storage mask. Default=1
|----
|RW
|[8]
|L2a FIFO storage mask. Default=1
|----
|RW
|[7:4]
|Unused
|----
|RW
|[3]
|L0 support. Default=1
|----
|RW
|[2]
|Enable RoI decoding. Default=0
|----
|RW
|[1]
|Disable_error_masking. Default=0
|----
|RW
|[0]
|Serial B channel on/off. Default=1
|----
|rowspan="6"|Control
|rowspan="6"|0x3001
|R
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|R
|[7:4]
|CDH version. Default=0x2
|----
|R
|[3]
|Not Used
|----
|R
|[2]
|Busy (receiving sequence) -
|----
|R
|[1]
|Run Active -
|----
|R
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|rowspan="2"|L1_Latency
|rowspan="2"|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info
|0x3051
|R
|[12:0]
|Latest Received Event information:
|----
|colspan="2" rowspan="10"|
|R
|[12]
|Include payload
|----
|R
|[11]
|Event has L2 Accept trigger
|----
|R
|[10]
|Event has L2 Reject trigger
|----
|R
|[9]
|Calibration trigger event
|----
|R
|[8]
|Software trigger event
|----
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|R
|[3]
|NA(=‘0’)
|----
|R
|[2]
|NA(=‘0’)
|----
|R
|[1]
|Region of Interest announced (=ESR)
|----
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x3053
|R
|[15:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="16"|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|R
|[14]
|Missing L1
|----
|R
|[13]
|Boundary L1
|----
|R
|[12]
|Spurious L1
|----
|R
|[11]
|Missing L0
|----
|R
|[10]
|Spurious L0
|----
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|Incomplete L2a Message
|----
|R
|[6]
|Incomplete L1 Message
|----
|R
|[5]
|Unknown Message Address Received
|----
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x3054
|R
|[8:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="9"|
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|L2 message content error
|----
|R
|[6]
|L1 message content error
|----
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|R
|[4]
|NA (= ‘0’)
|----
|R
|[3]
|NA (= ‘0’)
|----
|R
|[2]
|L2 message missing/timeout
|----
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related/BusyBox Registers

2009-11-19T14:12:32Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - 0x0 & RequestID(3:0) & OrbitID(23:16)
* Address ending "01" - OrbitID(15:0)
* Address ending "10" - 0x0 BunchCountID(11:0)
* Address ending "11" - DRORCID(7:0) & ChannelNumber(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="90"|Bit slice
!Description
|----
|rowspan="11"|Control
|rowspan="11"|0x3000
|RW
|[15:13]
|Unused
|----
|RW
|[12]
|Trigger Input Mask Enable. Default=0
|----
|RW
|[11]
|L1a message mask. Default=1
|----
|RW
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|RW
|[9]
|L2r FIFO storage mask. Default=1
|----
|RW
|[8]
|L2a FIFO storage mask. Default=1
|----
|RW
|[7:4]
|Unused
|----
|RW
|[3]
|L0 support. Default=1
|----
|RW
|[2]
|Enable RoI decoding. Default=0
|----
|RW
|[1]
|Disable_error_masking. Default=0
|----
|RW
|[0]
|Serial B channel on/off. Default=1
|----
|rowspan="6"|Control
|rowspan="6"|0x3001
|R
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|R
|[7:4]
|CDH version. Default=0x2
|----
|R
|[3]
|Not Used
|----
|R
|[2]
|Busy (receiving sequence) -
|----
|R
|[1]
|Run Active -
|----
|R
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|rowspan="2"|L1_Latency
|rowspan="2"|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info
|0x3051
|R
|[12:0]
|Latest Received Event information:
|----
|colspan="2" rowspan="10"|
|R
|[12]
|Include payload
|----
|R
|[11]
|Event has L2 Accept trigger
|----
|R
|[10]
|Event has L2 Reject trigger
|----
|R
|[9]
|Calibration trigger event
|----
|R
|[8]
|Software trigger event
|----
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|R
|[3]
|NA(=‘0’)
|----
|R
|[2]
|NA(=‘0’)
|----
|R
|[1]
|Region of Interest announced (=ESR)
|----
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x3053
|R
|[15:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="16"|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|R
|[14]
|Missing L1
|----
|R
|[13]
|Boundary L1
|----
|R
|[12]
|Spurious L1
|----
|R
|[11]
|Missing L0
|----
|R
|[10]
|Spurious L0
|----
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|Incomplete L2a Message
|----
|R
|[6]
|Incomplete L1 Message
|----
|R
|[5]
|Unknown Message Address Received
|----
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x3054
|R
|[8:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="9"|
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|L2 message content error
|----
|R
|[6]
|L1 message content error
|----
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|R
|[4]
|NA (= ‘0’)
|----
|R
|[3]
|NA (= ‘0’)
|----
|R
|[2]
|L2 message missing/timeout
|----
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related/BusyBox Registers

2009-11-09T09:00:10Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - DRORC Message(47:32)
* Address ending "01" - DRORC Message(31:16)
* Address ending "10" - DRORC Message(15:0)
* Address ending "11" - Receiving Channel number(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="90"|Bit slice
!Description
|----
|rowspan="11"|Control
|rowspan="11"|0x3000
|RW
|[15:13]
|Unused
|----
|RW
|[12]
|Trigger Input Mask Enable. Default=0
|----
|RW
|[11]
|L1a message mask. Default=1
|----
|RW
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|RW
|[9]
|L2r FIFO storage mask. Default=1
|----
|RW
|[8]
|L2a FIFO storage mask. Default=1
|----
|RW
|[7:4]
|Unused
|----
|RW
|[3]
|L0 support. Default=1
|----
|RW
|[2]
|Enable RoI decoding. Default=0
|----
|RW
|[1]
|Disable_error_masking. Default=0
|----
|RW
|[0]
|Serial B channel on/off. Default=1
|----
|rowspan="6"|Control
|rowspan="6"|0x3001
|R
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|R
|[7:4]
|CDH version. Default=0x2
|----
|R
|[3]
|Not Used
|----
|R
|[2]
|Busy (receiving sequence) -
|----
|R
|[1]
|Run Active -
|----
|R
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|rowspan="2"|L1_Latency
|rowspan="2"|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info
|0x3051
|R
|[12:0]
|Latest Received Event information:
|----
|colspan="2" rowspan="10"|
|R
|[12]
|Include payload
|----
|R
|[11]
|Event has L2 Accept trigger
|----
|R
|[10]
|Event has L2 Reject trigger
|----
|R
|[9]
|Calibration trigger event
|----
|R
|[8]
|Software trigger event
|----
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|R
|[3]
|NA(=‘0’)
|----
|R
|[2]
|NA(=‘0’)
|----
|R
|[1]
|Region of Interest announced (=ESR)
|----
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x3053
|R
|[15:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="16"|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|R
|[14]
|Missing L1
|----
|R
|[13]
|Boundary L1
|----
|R
|[12]
|Spurious L1
|----
|R
|[11]
|Missing L0
|----
|R
|[10]
|Spurious L0
|----
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|Incomplete L2a Message
|----
|R
|[6]
|Incomplete L1 Message
|----
|R
|[5]
|Unknown Message Address Received
|----
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x3054
|R
|[8:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="9"|
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|L2 message content error
|----
|R
|[6]
|L1 message content error
|----
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|R
|[4]
|NA (= ‘0’)
|----
|R
|[3]
|NA (= ‘0’)
|----
|R
|[2]
|L2 message missing/timeout
|----
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related

2009-10-28T09:28:00Z

St09909: /* Compiled BusyBox Firmware Versions */

Busy Box and related

2009-10-22T12:42:05Z

St09909: /* Compiled BusyBox Firmware Versions */

Busy Box and related/BusyBox Registers

2009-10-22T12:17:48Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - DRORC Message(47:32)
* Address ending "01" - DRORC Message(31:16)
* Address ending "10" - DRORC Message(15:0)
* Address ending "11" - Receiving Channel number(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="90"|Bit slice
!Description
|----
|rowspan="11"|Control
|rowspan="11"|0x3000
|RW
|[15:13]
|Unused
|----
|RW
|[12]
|Trigger Input Mask Enable. Default=0
|----
|RW
|[11]
|L1a message mask. Default=1
|----
|RW
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|RW
|[9]
|L2r FIFO storage mask. Default=1
|----
|RW
|[8]
|L2a FIFO storage mask. Default=1
|----
|RW
|[7:4]
|Unused
|----
|RW
|[3]
|L0 support. Default=1
|----
|RW
|[2]
|Enable RoI decoding. Default=0
|----
|RW
|[1]
|Disable_error_masking. Default=0
|----
|RW
|[0]
|Serial B channel on/off. Default=1
|----
|rowspan="6"|Control
|rowspan="6"|0x3001
|R
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|R
|[7:4]
|CDH version. Default=0x2
|----
|R
|[3]
|Not Used
|----
|R
|[2]
|Busy (receiving sequence) -
|----
|R
|[1]
|Run Active -
|----
|R
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|rowspan="2"|L1_Latency
|rowspan="2"|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info
|0x4051
|R
|[12:0]
|Latest Received Event information:
|----
|colspan="2" rowspan="10"|
|R
|[12]
|Include payload
|----
|R
|[11]
|Event has L2 Accept trigger
|----
|R
|[10]
|Event has L2 Reject trigger
|----
|R
|[9]
|Calibration trigger event
|----
|R
|[8]
|Software trigger event
|----
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|R
|[3]
|NA(=‘0’)
|----
|R
|[2]
|NA(=‘0’)
|----
|R
|[1]
|Region of Interest announced (=ESR)
|----
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x4053
|R
|[15:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="16"|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|R
|[14]
|Missing L1
|----
|R
|[13]
|Boundary L1
|----
|R
|[12]
|Spurious L1
|----
|R
|[11]
|Missing L0
|----
|R
|[10]
|Spurious L0
|----
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|Incomplete L2a Message
|----
|R
|[6]
|Incomplete L1 Message
|----
|R
|[5]
|Unknown Message Address Received
|----
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x4054
|R
|[8:0]
|Latest Received Event error conditions:
|----
|colspan="2" rowspan="9"|
|R
|[8]
|NA (= ‘0’)
|----
|R
|[7]
|L2 message content error
|----
|R
|[6]
|L1 message content error
|----
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|R
|[4]
|NA (= ‘0’)
|----
|R
|[3]
|NA (= ‘0’)
|----
|R
|[2]
|L2 message missing/timeout
|----
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related/BusyBox Registers

2009-10-22T11:41:25Z

St09909:

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Busy Box Status and Contol Registers
|-
!width="170"|Name
!Address
!Mode
!Description
!Default Value
|-
|TX module(15:0)
|0x0001
|RW
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|RX memory
|0x1000-0x1FFF
|RW
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - DRORC Message(47:32)
* Address ending "01" - DRORC Message(31:16)
* Address ending "10" - DRORC Message(15:0)
* Address ending "11" - Receiving Channel number(7:0)
|0x0000
|-
|RX memory pointer(13:0)
|0x2000
|R
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|EventID FIFO count(3:0)
|0x2001
|R
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|Current EventID(35:32)
|0x2002
|R
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|Current EventID(31:16)
|0x2003
|R
|0x0000
|-
|Current EventID(15:0)
|0x2004
|R
|0x0000
|-
|Newest EventID(35:32)
|0x2005
|R
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|Newest EventID(31:16)
|0x2006
|R
|0x0000
|-
|Newest EventID(15:0)
|0x2007
|R
|0x0000
|-
|L0 Trigger Timeout(15:0)
|0x2008
|RW
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|Busy Condition(15:0)
|0x2009
|RW
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|Halt FSM matching(0)
|0x200A
|RW
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|Force match(0)
|0x200B
|T
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|Re-Request Timeout(15:0)
|0x200C
|RW
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|Current RequestID(3:0)
|0x200D
|R
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|Retry Count(15:0)
|0x200E
|R
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|Busy time(31:16)
|0x2010
|R
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|Busy time(15:0)
|0x2011
|R
|0x0000
|-
|RX mem filter(15:0)
|0x2012
|RW
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|Number of Channels
|0x2014
|R
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|Firmware Revision
|0x2015
|R
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|Stresstest Enable(0)
|0x2016
|RW
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|Channel Registers
|0x21XX
|RW
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|-
|}

{|border="1" cellpadding="5" cellspacing="0"
!colspan="5"| Trigger Receiver Module Status and Control Registers
|-
!width="170"|Name
!Address
!Mode
!width="120"|Bit slice
!Description
|----
|Control
|0x3000
|RW
|[15:13]
|Unused
|----
|
|
|
|[12]
|Trigger Input Mask Enable. Default=0
|----
|
|
|
|[11]
|L1a message mask. Default=1
|----
|
|
|
|[10]
|L2 Timeout FIFO storage mask. Default=1
|----
|
|
|
|[9]
|L2r FIFO storage mask. Default=1
|----
|
|
|
|[8]
|L2a FIFO storage mask. Default=1
|----
|
|
|
|[7:4]
|Unused
|----
|
|
|
|[3]
|L0 support. Default=1
|----
|
|
|
|[2]
|Enable RoI decoding. Default=0
|----
|
|
|
|[1]
|Disable_error_masking. Default=0
|----
|
|
|
|[0]
|Serial B channel on/off. Default=1
|----
|Control
|0x3001
|
|[15:8]
|Trigger Receiver Version. Default=0x13
|----
|
|
|
|[7:4]
|CDH version. Default=0x2
|----
|
|
|
|[3]
|Not Used
|----
|
|
|
|[2]
|Busy (receiving sequence) -
|----
|
|
|
|[1]
|Run Active -
|----
|
|
|
|[0]
|Bunch_counter overflow -
|----
|Module Reset
|0x3002
|T
|N/A
|Reset Module
|----
|Reset Counters
|0x3008
|T
|N/A
|Write to this registers will reset the counters in the module
|----
|Issue Testmode
|0x300A
|T
|N/A
|Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.
|----
|L1_Latency
|0x300C
|RW
|[15:12]
|Uncertainty region +- N. default value 0x2 (50 ns)
|----
|
|
|RW
|[11:0]
|Latency from L0 to L1. default value 0x0D4 (5.3 us)
|----
|L2_Latency MAX
|0x300E
|RW
|[15:0]
|Max Latency from BC0 to L2. default value 0x4E20 (500 us)
|----
|L2_Latency MIN
|0x300F
|RW
|[15:0]
|Min Latency from BC0 to L2. default value 0x0C80 (80 us)
|----
|L1_msg_latency MAX
|0x3012
|RW
|[15:0]
|Max Latency from BC0 to L1 msg. default value 0x0028 (1 us)
|----
|L1_msg_latency MIN
|0x3013
|RW
|[15:0]
|Min Latency from BC0 to L1 msg. default value 0x0F8 (6.2 us)
|----
|Pre_pulse_counter
|0x3016
|R
|[15:0]
|Number of decoded pre-pulses.
|----
|BCID_Local
|0x3018
|R
|[11:0]
|Number of bunchcrossings at arrival of L1 trigger.
|----
|L0_counter
|0x301A
|R
|[15:0]
|Number of L0 triggers
|----
|L1_counter
|0x301C
|R
|[15:0]
|Number of L1 triggers
|----
|L1_msg_counter
|0x301E
|R
|[15:0]
|Number of successfully decoded L1 messages
|----
|L2a_counter
|0x3020
|R
|[15:0]
|Number of successfully decoded L2a messages
|----
|L2r_counter
|0x3022
|R
|[15:0]
|Number of successfully decoded L2r messages
|----
|Bunchcounter
|0x3026
|R
|[11:0]
|Debug: Number of bunchcrossings
|----
|SingleHammingErrorCnt
|0x302C
|R
|[15:0]
|Number of single bit hamming errors
|----
|DoubleHammingErrorCnt
|0x302D
|R
|[15:0]
|Number of double bit hamming errors
|----
|MsgDecodingErrorCnt
|0x302E
|R
|[15:0]
|Number of message decoding errors
|----
|SeqTimoutErrorCnt
|0x302F
|R
|[15:0]
|Number of errors related to sequence and timeouts.
|----
|Buffered_events
|0x3040
|R
|[4:0]
|Number of events stored in the FIFO.
|----
|DAQ_Header01
|0x3042
|R
|[15:0]
|Latest received DAQ Header 1 [15:0]
|----
|DAQ_Header01
|0x3043
|R
|[15:0]
|Latest received DAQ Header 1 [31:16]
|----
|DAQ_Header02
|0x3044
|R
|[15:0]
|Latest received DAQ Header 2 [15:0]
|----
|DAQ_Header02
|0x3045
|R
|[15:0]
|Latest received DAQ Header 2 [31:16]
|----
|DAQ_Header03
|0x3046
|R
|[15:0]
|Latest received DAQ Header 3 [15:0]
|----
|DAQ_Header03
|0x3047
|R
|[15:0]
|Latest received DAQ Header 3 [31:16]
|----
|DAQ_Header04
|0x3048
|R
|[15:0]
|Latest received DAQ Header 4 [15:0]
|----
|DAQ_Header04
|0x3049
|R
|[15:0]
|Latest received DAQ Header 4 [31:16]
|----
|DAQ_Header05
|0x304a
|R
|[15:0]
|Latest received DAQ Header 5 [15:0]
|----
|DAQ_Header05
|0x304b
|R
|[15:0]
|Latest received DAQ Header 5 [31:16]
|----
|DAQ_Header06
|0x304c
|R
|[15:0]
|Latest received DAQ Header 6 [15:0]
|----
|DAQ_Header06
|0x304d
|R
|[15:0]
|Latest received DAQ Header 6 [31:16]
|----
|DAQ_Header07
|0x304e
|R
|[15:0]
|Latest received DAQ Header 7 [15:0]
|----
|DAQ_Header07
|0x304f
|R
|[15:0]
|Latest received DAQ Header 7 [31:16]
|----
|Event_info[17:0]
|0x4028
|R
|[12:0]
|Latest Received Event information:
|----
|
|
|R
|[12]
|Include payload
|----
|
|
|R
|[11]
|Event has L2 Accept trigger
|----
|
|
|R
|[10]
|Event has L2 Reject trigger
|----
|
|
|R
|[9]
|Calibration trigger event
|----
|
|
|R
|[8]
|Software trigger event
|----
|
|
|R
|[4:7]
|Calibration/SW trigger type (= RoC)
|----
|
|
|R
|[3]
|NA(=‘0’)
|----
|
|
|R
|[2]
|NA(=‘0’)
|----
|
|
|R
|[1]
|Region of Interest announced (=ESR)
|----
|
|
|R
|[0]
|NA(=’0’)
|----
|Event_error
|0x4029
|R
|[15:0]
|Latest Received Event error conditions:
|----
|
|
|R
|[15]
|L1 message arrives outside legal timeslot
|----
|
|
|R
|[14]
|Missing L1
|----
|
|
|R
|[13]
|Boundary L1
|----
|
|
|R
|[12]
|Spurious L1
|----
|
|
|R
|[11]
|Missing L0
|----
|
|
|R
|[10]
|Spurious L0
|----
|
|
|R
|[9]
|TTCrx Address Error (not X”0003”)
|----
|
|
|R
|[8]
|NA (= ‘0’)
|----
|
|
|R
|[7]
|Incomplete L2a Message
|----
|
|
|R
|[6]
|Incomplete L1 Message
|----
|
|
|R
|[5]
|Unknown Message Address Received
|----
|
|
|R
|[4]
|Double Bit Hamming Error Broadcast.
|----
|
|
|R
|[3]
|Single Bit Hamming Error Broadcast.
|----
|
|
|R
|[2]
|Double Bit Hamming Error Individually Addr.
|----
|
|
|R
|[1]
|Single Bit Hamming Error Individually Addr.
|----
|
|
|R
|[0]
|Serial B Stop Bit Error
|----
|Event_error
|0x4029
|R
|[8:0]
|Latest Received Event error conditions:
|----
|
|
|R
|[8]
|NA (= ‘0’)
|----
|
|
|R
|[7]
|L2 message content error
|----
|
|
|R
|[6]
|L1 message content error
|----
|
|
|R
|[5]
|Prepulse error (=0; possible future use)
|----
|
|
|R
|[4]
|NA (= ‘0’)
|----
|
|
|R
|[3]
|NA (= ‘0’)
|----
|
|
|R
|[2]
|L2 message missing/timeout
|----
|
|
|R
|[1]
|L2 message arrives outside legal timeslot
|----
|
|
|R
|[0]
|L1 message missing/timeout
|----
|}

Busy Box and related/BusyBox Registers

2009-10-22T08:29:11Z

St09909:

Busy Box and related/BusyBox Registers

2009-10-21T10:12:34Z

St09909:

Busy Box and related/BusyBox Registers

2009-10-21T09:06:20Z

St09909: /* Busy Box Status and Contol Registers */

{| border="1" cellpadding="1" cellspacing="0" |colspan="5"|
{| border="1" cellpadding="1" cellspacing="0" |colspan="5"|
====Busy Box Status and Contol Registers====
|-
!Address
!Mode
!width="170"|Name
!Description
!Default Value
|-
|0x0001
|RW
|TX module(15:0)
|For sending messages to DRORCs.
* Bit 7:0 is TX data.
* Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|0x1000-0x1FFF
|RW
|RX memory
|Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
* Address ending "00" - DRORC Message(47:32)
* Address ending "01" - DRORC Message(31:16)
* Address ending "10" - DRORC Message(15:0)
* Address ending "11" - Receiving Channel number(7:0)
|0x0000
|-
|0x2000
|R
|RX memory pointer(13:0)
|Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message.
|0x0000
|-
|0x2001
|R
|EventID FIFO count(3:0)
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|0x2002
|R
|Current EventID(35:32)
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|0x2003
|R
|Current EventID(31:16)
|0x0000
|-
|0x2004
|R
|Current EventID(15:0)
|0x0000
|-
|0x2005
|R
|Newest EventID(35:32)
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|0x2006
|R
|Newest EventID(31:16)
|0x0000
|-
|0x2007
|R
|Newest EventID(15:0)
|0x0000
|-
|0x2008
|RW
|L0 Trigger Timeout(15:0)
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|0x2009
|RW
|Busy Condition(15:0)
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 11:8 - Unused
* Bit 7:4 - Current MEB count.
* Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|0x200A
|RW
|Halt FSM matching(0)
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|0x200B
|T
|Force match(0)
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|0x200C
|RW
|Re-Request Timeout(15:0)
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|0x200D
|R
|Current RequestID(3:0)
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|0x200E
|R
|Retry Count(15:0)
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|0x2010
|R
|Busy time(31:16)
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|0x2011
|R
|Busy time(15:0)
|0x0000
|-
|0x2012
|RW
|RX mem filter(15:0)
|Allows filtering of messages that are stored in RX memory.
*Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15:8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|0x2014
|R
|Number of Channels
|Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time.
|N/A
|-
|0x2015
|R
|Firmware Revision
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|0x2016
|RW
|Stresstest Enable(0)
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|0x21XX
|RW
|Channel Registers
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|}

Busy Box and related/BusyBox Registers

2009-10-21T08:40:40Z

St09909:

{| border="1" cellpadding="1" cellspacing="0" |colspan="5"|
====Busy Box Status and Contol Registers====
|-
!Address
!Mode
!width="170"|Name
!Description
!Default Value
|-
|0x0001
|RW
|TX module
|For sending messages to DRORCs.
* Bit 7-0 is TX data.
* Bit 15-8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|0x0000
|-
|0x1XXX
|RW
|RX memory
|Memory where all messages received from DRORCs will be stored.
|0x0000
|-
|0x2000
|R
|RX memory pointer
|Holds the value where the next message will be written in RX memory.
|0x0000
|-
|0x2001
|R
|EventID FIFO count
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|0x0000
|-
|0x2002
|R
|Current EventID(35-32)
|rowspan="3"|The EventID which is currently being matched.
|0x0000
|-
|0x2003
|R
|Current EventID(31-16)
|0x0000
|-
|0x2004
|R
|Current EventID(15- 0)
|0x0000
|-
|0x2005
|R
|Newest EventID(35-32)
|rowspan="3"|The EventID most recently received from the Trigger system.
|0x0000
|-
|0x2006
|R
|Newest EventID(31-16)
|0x0000
|-
|0x2007
|R
|Newest EventID(15- 0)
|0x0000
|-
|0x2008
|RW
|L0 Trigger Timeout
|Time in 10 us resolution the 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|0x000A
|-
|0x2009
|RW
|Busy Condition
|Status and control registers concerning the BUSY generation
* Bit 15 - Busy because TTCrx_ready is low.
* Bit 14 - Busy because MEB count >= MEB limit
* Bit 13 - Busy because L0 timeout is active.
* Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
* Bit 7-4 - Current MEB count.
* Bit 3-0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
|0x0000
|-
|0x200A
|RW
|Halt FSM matching
|If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs.
|0x0001
|-
|0x200B
|T
|Force match
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect.
|N/A
|-
|0x200C
|RW
|Re-Request Timeout
|Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs.
|0x07FF
|-
|0x200D
|R
|Current RequestID
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|0x0000
|-
|0x200E
|R
|Retry Count(15-0)
|Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID.
|0x0000
|-
|0x2010
|R
|Busy time(31-16)
|rowspan="2"|Holds value of counter for number of clock cycles BUSY has been asserted.
|0x0000
|-
|0x2011
|R
|Busy time(15-0)
|0x0000
|-
|0x2012
|RW
|RX mem filter
|Allows filtering of messages that are stored in RX memory.
*Bit 7-0 is the pattern that will be matched with the channelnumber of the message.
*Bit 15-8 allows enableing matching of individual bits 7-0.
|0x0000
|-
|0x2015
|R
|Firmware Revision
|Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 34
|0x0022
|-
|0x2016
|RW
|Stresstest Enable(0)
|Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available.
|0x0000
|-
|0x21XX
|RW
|Channel Registers
|'XX' in the address gives the channelnumber in hexadecimal.
*Bit 0 is enable(1)/disable(0)
*Bit 1 indicates that the current EventID has been matched on this channel.
|0x0001
|}

Busy Box and related

2009-10-20T15:11:35Z

St09909: /* BusyBox Firmware */

Busy Box and related

2009-10-20T15:10:15Z

St09909: /* BusyBox Firmware */

Busy Box and related

2009-10-20T15:09:42Z

St09909: /* BusyBox Firmware */

Busy Box and related/BusyBoxRegisters

2009-10-20T15:06:12Z

St09909: moved Busy Box and related/BusyBoxRegisters to Busy Box and related/BusyBox Registers

#REDIRECT [[Busy Box and related/BusyBox Registers]]

Busy Box and related/BusyBox Registers

2009-10-20T15:06:12Z

St09909: moved Busy Box and related/BusyBoxRegisters to Busy Box and related/BusyBox Registers

{| border="1" cellpadding="1" cellspacing="0"
|colspan="5"|
====Busy Box Status and Contol Registers====
|-
!Address
!Read/Write
!Name
!Description
!Default Value
|-
|0x0001
|RW
|TX module
|For sending messages to DRORCs. Bit 7-0 is TX data. Bit 15-8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
|TBD
|-
|0x1XXX
|RW
|RX memory
|Memory where all messages received from DRORCs will be stored.
|TBD
|-
|0x2000
|R
|RX memory pointer
|Holds the value where the next message will be written in RX memory.
|TBD
|-
|0x2001
|R
|EventID count
|Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any.
|TBD
|-
|0x2002
|R
|Current EventID(35-32)
|The EventID which is currently being matched.
|TBD
|-
|0x2003
|R
|Current EventID(31-16)
|
|TBD
|-
|0x2004
|R
|Current EventID(15- 0)
|
|TBD
|-
|0x2005
|R
|Newest EventID(35-32)
|The EventID most recently received from the TTC system.
|TBD
|-
|0x2006
|R
|Newest EventID(31-16)
|
|TBD
|-
|0x2007
|R
|Newest EventID(15- 0)
|
|TBD
|-
|0x2008
|RW
|L0 trigger timeout
|Number of clock cycles 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full.
|TBD
|-
|0x2009
|RW
|FEE buffers available
|Config: Holds the number buffers assumed on the FEE.
|TBD
|-
|0x200A
|RW
|Halt FW matching
|If LSB is set to 1 the internal FSM will halt in a wait state.
|TBD
|-
|0x200B
|w
|Force match
|Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched.
|TBD
|-
|0x200C
|RW
|Re-Request Timeout
|Number of clock cycles to wait in between sending requests to the DRORCs.
|TBD
|-
|0x200D
|R
|Current RequestID
|Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs.
|TBD
|-
|0x200E
|R
|Retry Count
|Number of times requests have been sent to DRORCs.
|TBD
|-
|0x2010
|R
|Busy time(31-16)
|Holds value of counter for number of clock
|TBD
|-
|0x2011
|R
|Busy time(15- 0)
|cycles BUSY has been asserted.
|TBD
|-
|0x2012
|RW
|RX mem filter
|Allows filtering of messages that are stored in RX memory. Bit 7-0 is the pattern that will be matched with the channelnumber of the message. Bit 15-8 allows enableing matching of individual bits 7-0.
|TBD
|-
|0x21XX
|RW
|Channel Registers
|'XX' in the address gives the channelnumber in hexadecimal. Bit 0 is enable/disable (0/1) Bit 1 indicates that the current EventID has been matched on this channel.
|TBD
|}

Busy Box and related/BusyBox Registers

2009-10-20T15:02:49Z

St09909: Created page with '{| border="1" cellpadding="1" cellspacing="0" |colspan="5"| ====Busy Box Status and Contol Registers==== |- !Address !Read/Write !Name !Description !Default Value |- |0x0001 |RW ...'

Busy Box and related

2009-10-14T11:34:07Z

St09909: /* BusyBox Firmware */

Busy Box and related

2009-10-14T11:31:31Z

St09909: /* Compiled BusyBox Firmware Versions */

Busy Box and related

2009-10-14T11:10:01Z

St09909: /* DCS board firmware for BusyBox */

Busy Box and related

2009-10-14T09:58:08Z

St09909: /* Generating FPGA configuration files from source code */

Busy Box and related

2009-10-14T09:40:37Z

St09909: /* BusyBox Firmware */

Busy Box and related

2009-10-14T08:13:11Z

St09909: /* Download Section */

Busy Box and related

2009-10-14T08:12:33Z

St09909: /* BusyBox Hardware tests at UiB */

Busy Box and related

2009-10-14T08:06:15Z

St09909: /* Compiled BusyBox Firmware Versions */

Busy Box and related

2009-10-14T08:01:33Z

St09909: /* Download Section */

Busy Box and related

2009-10-14T07:45:00Z

St09909: /* How to run the RCU - DRORC - Busybox setup */

Busy Box and related

2009-10-09T14:56:23Z

St09909: