ift - User contributions [en]

Using the VGA controller with block ram generator and clock wizard

2016-03-02T23:33:10Z

Nas005:

If you want to use the vga controller remember to
* copy-paste the vga.txt file and save it as vga.vhd
* copy-paste the Nexys4_Master.txt file and save it as Nexys4_Master.xdc

The vga controller is using a BRAM block to store pixel values. Each pixel has 12-bits and number of pixels projected to the screen is 480x640=307200
* sw_i(15) -- active high, write enable
* sw_i(11 downto 0) -- 12-bits for colour changing the screen

CREATING NEW PROJECT

Press create new project
[[File:16.png|400px]]

Press next on the first window that pops up, then you can choose were you want to store your project, click next.
[[File:17.png|400px]]

Choose RTL project and click next
[[File:18.png|400px]]

Add your VHDL file if you have one, if you don’t you can add the VGA-controller file just to make sure that everything works properly. Click next
[[File:19.png|400px]]

Click next
[[File:20.png|400px]]

Add the Nexys4_Master.xdc , this will connect all your I/O, LED, SW etc.
[[File:21.png|400px]]

Choose the xca100tcsg324-1 and click next and then finish.
[[File:22.png|400px]]

Vivado will open, now you can make your own VHDL code or you can follow instruction further if you want to use the VGA controller. If you want to make your own code you can skip the IP part and go to generate bitstream to see how you should implement your code on the FPGA.
[[File:23.png|400px]]

Adding IP’s, clk generator 25.2MHz and BRAM. Click IP Catalog and then
[[File:24.png|400px]]

Search for Clocking Wizard and enter and this will pop up, clocking option should look like this, remember to change the Component name!
[[File:25.png|400px]]

Change the output clock to 25.2MHz
[[File:26.png|400px]]

Port renaming: use names that explains your component, and click OK
[[File:27.png|400px]]

This should pop up, click generate
[[File:28.png|400px]]

Adding BRAM, search for bram and enter the Block Memory Generator and this should pop up. Remember component name
[[File:29.png|400px]]

Port A Options, write width = 12bits, write depth = 307200=(480*640 pixels projected on screen), then click OK and then generate as before and wait until the synthesis is done.
[[File:30.png|400px]]

GENERATE BITSTREAM: click generate bitstream
[[File:31.png|400px]]

If this pops up click yes
[[File:32.png|400px]]

If this message shows, just click ok, it only means that you have pins activated in your Nexys4_Master.xdc that are not in use.
[[File:33.png|400px]]

If later on want to change witch pins are active on your board you can configure this by entering the Nexys4_Master.xdc
[[File:34.png|400px]]

When completed, choose “Open Hardware Manager” and click ok
[[File:35.png|400px]]

At this point connect your NEXY4 board . In the left menu under “program and debug”, click open target => open new target
[[File:36.png|400px]]

Open new Hardware target will pop up, click next two times and this will show. Choose JTAG clock freq. 30 000 000, click next and then finish
[[File:37.png|400px]]

Now you can program your device, click program device and choose your FPGA
[[File:38.png|400px]]

Click program and your device is ready to go.
[[File:39.png|400px]]

Using the VGA controller with block ram generator and clock wizard

2016-03-02T23:21:55Z

Nas005: Created page with "If you want to use the vga controller remember to * copy-paste the vga.txt file and save it as vga.vhd * copy-paste the Nexys4_Master.txt file and save it as Nexys4_Master.x..."

If you want to use the vga controller remember to
* copy-paste the vga.txt file and save it as vga.vhd
* copy-paste the Nexys4_Master.txt file and save it as Nexys4_Master.xdc

CREATING NEW PROJECT

Press create new project
[[File:16.png|400px]]

Press next on the first window that pops up, then you can choose were you want to store your project, click next.
[[File:17.png|400px]]

Choose RTL project and click next
[[File:18.png|400px]]

Add your VHDL file if you have one, if you don’t you can add the VGA-controller file just to make sure that everything works properly. Click next
[[File:19.png|400px]]

Click next
[[File:20.png|400px]]

Add the Nexys4_Master.xdc , this will connect all your I/O, LED, SW etc.
[[File:21.png|400px]]

Choose the xca100tcsg324-1 and click next and then finish.
[[File:22.png|400px]]

Vivado will open, now you can make your own VHDL code or you can follow instruction further if you want to use the VGA controller. If you want to make your own code you can skip the IP part and go to generate bitstream to see how you should implement your code on the FPGA.
[[File:23.png|400px]]

Adding IP’s, clk generator 25.2MHz and BRAM. Click IP Catalog and then
[[File:24.png|400px]]

Search for Clocking Wizard and enter and this will pop up, clocking option should look like this, remember to change the Component name!
[[File:25.png|400px]]

Change the output clock to 25.2MHz
[[File:26.png|400px]]

Port renaming: use names that explains your component, and click OK
[[File:27.png|400px]]

This should pop up, click generate
[[File:28.png|400px]]

Adding BRAM, search for bram and enter the Block Memory Generator and this should pop up. Remember component name
[[File:29.png|400px]]

Port A Options, write width = 12bits, write depth = 307200=(480*640 pixels projected on screen), then click OK and then generate as before and wait until the synthesis is done.
[[File:30.png|400px]]

GENERATE BITSTREAM: click generate bitstream
[[File:31.png|400px]]

If this pops up click yes
[[File:32.png|400px]]

If this message shows, just click ok, it only means that you have pins activated in your Nexys4_Master.xdc that are not in use.
[[File:33.png|400px]]

If later on want to change witch pins are active on your board you can configure this by entering the Nexys4_Master.xdc
[[File:34.png|400px]]

When completed, choose “Open Hardware Manager” and click ok
[[File:35.png|400px]]

At this point connect your NEXY4 board . In the left menu under “program and debug”, click open target => open new target
[[File:36.png|400px]]

Open new Hardware target will pop up, click next two times and this will show. Choose JTAG clock freq. 30 000 000, click next and then finish
[[File:37.png|400px]]

Now you can program your device, click program device and choose your FPGA
[[File:38.png|400px]]

Click program and your device is ready to go.
[[File:39.png|400px]]

File:39.png

2016-03-02T23:07:06Z

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Nexys4 Master.xdc

2016-03-02T23:04:36Z

Nas005: Created page with ":File:Nexys4_Master.txt"

[[:File:Nexys4_Master.txt]]

File:Nexys4 Master.txt

2016-03-02T23:04:26Z

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VGA controller VHDL code

2016-03-02T22:57:24Z

Nas005: Replaced content with ":File:vga.txt"

[[:File:vga.txt]]

File:Vga.txt

2016-03-02T22:56:46Z

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VGA controller VHDL code

2016-03-02T22:51:24Z

Nas005: Created page with "library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Vga is Port ( clk_i : in STD_LOGIC; sw_i :..."

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Vga is
Port ( clk_i : in STD_LOGIC;
sw_i : in STD_LOGIC_VECTOR (15 downto 0); -- (11 downto 8) is RED, (7 downto 4) is GREEN, (3 downto 0) is BLUE
-- Writing directly to RAM and from RAM to VGA interface.
-- Writing when sw_i(15) is high
-- VGA Output Signals
vga_hs_o : out STD_LOGIC; -- Horizontal sync puls to VGA interface
vga_vs_o : out STD_LOGIC; -- Vertical sync puls to VGA interface
vga_red_o : out STD_LOGIC_VECTOR (3 downto 0); -- Red to VGA interface
vga_green_o : out STD_LOGIC_VECTOR (3 downto 0); -- Green to VGA interface
vga_blue_o : out STD_LOGIC_VECTOR (3 downto 0) -- Blue to VGA interface
);
end Vga;

architecture Behavioral of Vga is

-------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------

-- 25.2MHz Clock
COMPONENT clk_wiz_25_2MHz
PORT (
clk_in_100MHz: in STD_LOGIC;
clk_out_25_2: out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC
);
END COMPONENT;

-- Ram block for pixels
COMPONENT PIX_RAM
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
);
END COMPONENT;

-------------------------------------------------------------
-- Constants for VGA Resolutions
-------------------------------------------------------------

------640x480 60Hz-------
constant WIDTH : natural := 640;
constant HEIGHT : natural := 480;

constant H_FP : natural := 16; --H front porch width (pixels)
constant H_PW : natural := 96; --H sync pulse width (pixels)
constant H_TOT : natural := 800; --H total period (pixels)

constant V_FP : natural := 10; --V front porch width (lines)
constant V_PW : natural := 2; --V sync pulse width (lines)
constant V_TOT : natural := 525; --V total period (lines)

-------------------------------------------------------------------------
-- VGA signals: Counters, Sync, Red, Gree, Blue
-------------------------------------------------------------------------

-- Activates the screen when it is in the frame area
signal SCREEN_ON : std_logic;

-- Horizontal and Vertical counters
signal h_count : std_logic_vector(11 downto 0) := (others =>'0');
signal v_count : std_logic_vector(11 downto 0) := (others =>'0');

-- signal for the VGA interface
signal vga_red : std_logic_vector(3 downto 0);
signal vga_blue : std_logic_vector(3 downto 0);
signal vga_green : std_logic_vector(3 downto 0);

-------------------------------------------------------------------------
-- CLOCK signals
-------------------------------------------------------------------------
signal pxl_clk: std_logic; -- pxl_clk is 25.2MHz
signal reset: std_logic := '0';

-------------------------------------------------------------------------
-- RAM signals
-------------------------------------------------------------------------

signal data_out : std_logic_vector(11 downto 0) := (others =>'0');
signal data_inn : std_logic_vector(11 downto 0) := (others =>'0');
signal address : std_logic_vector(18 downto 0) := (others =>'0');
signal write : std_logic_vector(0 downto 0) ;

begin

---------------------------
-- PORT MAPS
---------------------------

-- PIXELGENERATOR - pxl_clk=25.2MHz
PIXELGENERATOR : clk_wiz_25_2MHz PORT MAP
(--clock inn
clk_in_100MHz => clk_i,
--clock out
clk_out_25_2 => pxl_clk,
--reset active high
reset => reset,
--status and controll signals
locked => open
);

-- RAM
RAM : PIX_RAM PORT MAP
(
clka => clk_i,
ena => '1',
wea => write,
addra => address,
dina => data_inn,
douta => data_out
);

-----------------------------------------------------------------
-- Generate Horizontal, Vertical counters and the Sync signals
-----------------------------------------------------------------
-- Horizontal counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_count = (H_TOT - 1)) then
h_count <= (others =>'0');
else
h_count <= h_count + 1;
end if;
end if;
end process;

-- Vertical counter
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if ((h_count = (H_TOT - 1)) and (v_count = (V_TOT - 1))) then
v_count <= (others =>'0');
elsif (h_count = (H_TOT - 1)) then
v_count <= v_count + 1;
end if;
end if;
end process;

-- Horizontal sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (h_count >= (H_FP + WIDTH - 1)) and (h_count < (H_FP + WIDTH + H_PW - 1)) then
vga_hs_o <= '1';
else
vga_hs_o <= '0';
end if;
end if;
end process;

-- Vertical sync
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if (v_count >= (V_FP + HEIGHT - 1)) and (v_count < (V_FP + HEIGHT + V_PW - 1)) then
vga_vs_o <= '1';
else
vga_vs_o <= '0';
end if;
end if;
end process;

-------------------------------------------------------
-- RAM interface
-------------------------------------------------------
-- Synchronizing reading and writing of adresses with the VGA interface
process (pxl_clk)
begin
if (rising_edge(pxl_clk)) then
if h_count < WIDTH and v_count < HEIGHT then
address <= address + 1;
else
address <= (others =>'0');
end if;
end if;
end process;

--------------------
-- SCREEN ON
--------------------
-- screening signal
SCREEN_ON <= '1' when h_count < WIDTH and v_count < HEIGHT
else '0';

------------------------------------------------------------
-- Turn Off VGA RBG Signals if outside of the active screen
-- Make a 4-bit AND logic with the R, G and B signals
------------------------------------------------------------

vga_red_o <= (SCREEN_ON & SCREEN_ON & SCREEN_ON & SCREEN_ON) and vga_red;
vga_green_o <= (SCREEN_ON & SCREEN_ON & SCREEN_ON & SCREEN_ON) and vga_green;
vga_blue_o <= (SCREEN_ON & SCREEN_ON & SCREEN_ON & SCREEN_ON) and vga_blue;

--------------------
-- Rerouting signals
--------------------
vga_red <= data_out(11 downto 8);
vga_green <= data_out(7 downto 4);
vga_blue <= data_out(3 downto 0);

data_inn <= sw_i(11 downto 0); -- (11 downto 8) is RED, (7 downto 4) is GREEN, (3 downto 0) is BLUE
write <= sw_i(15 downto 15); -- Activ high when writing to BRAM

end Behavioral;

Install Vivado 2015.4 with free licens

2016-03-02T22:48:07Z

Nas005:

To download Vivado for free you must first create an account. By following this link [http://www.xilinx.com/support/download.html/ Xilinx web page] you will enter Xilinx download page. For this tutorial we will be using the 2015.4 version.

To download for Windows
Vivado HLx 2015.4 Web Install for Windows with SDK (EXE - 49.32 MB)

For linux
Vivado HLx 2015.4 Web Install for Linux with SDK (BIN - 76.98 MB)

Run the installer and this will show, press next
[[File:1.png]]

Type your user name and password and press next
[[File:2.png]]

Agree to everything!!! Or else?!?!
[[File:3.png]]

Choose Vivado HL WebPACK
[[File:4.png]]

Make sure the Software Development Kit, Artix-7, Install Cable Drivers, and Acquire or Manage a License Key are all checked and click next.
The DocNav file is not necessary but it allows you to
* Find answers to your questions quickly through the integrated search
* Manage documents on your desktop through the Download Manager
* Always ensures you are reading the latest version of documentation
Detailed information about using the tool and its features can be found in the Online Help Menu which you can access after installation.
[[File:5.png]]

Choose a directory to Install you Vivado product, make sure you have adequate free space on your hard drive.
[[File:6.png]]

The final screen summarizes your selections. Click install, and the installer will begin downloading the files it needs to install Vivado. When it is done this screen will pop up.
[[File:7.png]]

Click ok and the license manager should open up.
If not open Vivado press Help=>obtain a license key and this window will open.
Choose “Get Free SDK, Vivado WebPACK” and then press Connect Now.
[[File:8.png]]

You will be redirected to Xilinx home page were you will need to sign in with user name and password. After clicking “sign in”, press “next” and this site will pop up
[[File:9.png]]

Choose “Vivado Design Suite: HL WebPACK, Node-Locked License……..” and press Generate Node-Locked License. Next this window will pop up.
[[File:10.png]]

Click next and a new window will pop up, click next again and this will show
[[File:11.png]]

Open your E-mail and download the attached Xilinx.lic file. When you go back to the license manager this will show, press cancel.
[[File:12.png]]

Go to Load License in the left menu. You should see this
[[File:13.png]]

Click Copy License and upload the Xilinx.lic file and you will get this message
[[File:14.png]]

If you now press the view license status in the left menu, you should see this
[[File:15.png]]

You can now close the license manager and Vivado is good to go.

Install Vivado 2015.4 with free licens

2016-03-02T22:39:08Z

Nas005: Created page with "To download Vivado for free you must first create an account. By following this link [http://www.xilinx.com/support/download.html/ Xilinx web page] you will enter Xilinx dow..."

To download Vivado for free you must first create an account. By following this link [http://www.xilinx.com/support/download.html/ Xilinx web page] you will enter Xilinx download page. For this tutorial we will be using the 2015.4 version.

To download for Windows
Vivado HLx 2015.4 Web Install for Windows with SDK (EXE - 49.32 MB)

For linux
Vivado HLx 2015.4 Web Install for Linux with SDK (BIN - 76.98 MB)
Run the installer and this will show, press next
[[File:1.png]]

Type your user name and password and press next
[[File:2.png]]

Agree to everything!!! Or else?!?!

[[File:3.png]]

Choose Vivado HL WebPACK

[[File:4.png]]

Make sure the Software Development Kit, Artix-7, Install Cable Drivers, and Acquire or Manage a License Key are all checked and click next. The DocNav file is not necessary but it allows you to
• Find answers to your questions quickly through the integrated search
• Manage documents on your desktop through the Download Manager
• Always ensures you are reading the latest version of documentation
Detailed information about using the tool and its features can be found in the Online Help Menu which you can access after installation.

[[File:5.png]]
[[File:6.png]]
[[File:7.png]]
[[File:8.png]]
[[File:9.png]]
[[File:10.png]]
[[File:11.png]]
[[File:12.png]]
[[File:13.png]]
[[File:14.png]]
[[File:15.png]]

Choose a directory to Install you Vivado product, make sure you have adequate free space on your hard drive.

The final screen summarizes your selections. Click install, and the installer will begin downloading the files it needs to install Vivado. When it is done this screen will pop up.

Click ok and the license manager should open up.
If not open Vivado press Help=>obtain a license key and this window will open.
Choose “Get Free SDK, Vivado WebPACK” and then press Connect Now.
.

You will be redirected to Xilinx home page were you will need to sign in with user name and password. After clicking “sign in”, press “next” and this site will pop up

Choose “Vivado Design Suite: HL WebPACK, Node-Locked License……..” and press Generate Node-Locked License. Next this window will pop up.

Click next and a new window will pop up, click next again and this will show

Open your E-mail and download the attached Xilinx.lic file. When you go back to the license manager this will show, press cancel.

Go to Load License in the left menu. You should see this

Click Copy License and upload the Xilinx.lic file and you will get this message

If you now press the view license status in the left menu, you should see this

You can now close the license manager and Vivado is good to go.

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PHYS321

2016-03-02T22:32:08Z

Nas005: /* Vivado 2015.4 Install with free licens */

== Fagressurser for bruk i PHYS321 ==

=== Fagbøker ===
* [http://site.ebrary.com/lib/bergen/docDetail.action?docID=10053265 Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits]

=== Nettressurser ===
* [http://klabs.org/richcontent/Tutorial/tutorial.htm Tutorials for Programmable Logic and Military/Aerospace Systems]
* [http://www.ecs.umass.edu/ece/koren/arith/simulator/ Arithmetic Algorithms Simulators]
* [http://en.wikipedia.org/wiki/Linear_feedback_shift_register Linear feedback shift register]

==== Cadence tutorials ====
* [http://www-classes.usc.edu/engr/ee-s/477p/cadencetutorial.pdf Inverter eksempel]
* [https://www.youtube.com/watch?v=DPCu822wXPQ Inverter eksempel 1 youtube]
* [https://www.youtube.com/watch?v=AIjGRzNIWC4 Inverter eksempel 2 youtube]
* [https://www.youtube.com/watch?v=mQm88hoskkw Inverter eksempel 3 youtube]

=== Øvingsoppgaver ===
[[Øvingsoppgaver PHYS321]]

==== Digilent Nexys 4 ====
* [https://reference.digilentinc.com/vivado:installation Install Vivado with free licence]
* [https://reference.digilentinc.com/nexys:nexys4:gsg Getting started]
* [https://reference.digilentinc.com/vivado Vivado - Xilinx Programming Environment - Board files, reference projects, etc]
* [https://reference.digilentinc.com/nexys:nexys4:start Nexys 4 Resource center]

==== Using Vivado ====

* [[Install Vivado 2015.4 with free licens]]
* [[VGA controller VHDL code]]
* [[Nexys4_Master.xdc]]
* [[Using the VGA controller with block ram generator and clock wizard]]

[[Category:Mikroelektronikk]]

PHYS321

2016-03-02T22:17:54Z

Nas005: /* Vivado 2015.4 Install with free licens */

== Fagressurser for bruk i PHYS321 ==

=== Fagbøker ===
* [http://site.ebrary.com/lib/bergen/docDetail.action?docID=10053265 Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits]

=== Nettressurser ===
* [http://klabs.org/richcontent/Tutorial/tutorial.htm Tutorials for Programmable Logic and Military/Aerospace Systems]
* [http://www.ecs.umass.edu/ece/koren/arith/simulator/ Arithmetic Algorithms Simulators]
* [http://en.wikipedia.org/wiki/Linear_feedback_shift_register Linear feedback shift register]

==== Cadence tutorials ====
* [http://www-classes.usc.edu/engr/ee-s/477p/cadencetutorial.pdf Inverter eksempel]
* [https://www.youtube.com/watch?v=DPCu822wXPQ Inverter eksempel 1 youtube]
* [https://www.youtube.com/watch?v=AIjGRzNIWC4 Inverter eksempel 2 youtube]
* [https://www.youtube.com/watch?v=mQm88hoskkw Inverter eksempel 3 youtube]

=== Øvingsoppgaver ===
[[Øvingsoppgaver PHYS321]]

==== Digilent Nexys 4 ====
* [https://reference.digilentinc.com/vivado:installation Install Vivado with free licence]
* [https://reference.digilentinc.com/nexys:nexys4:gsg Getting started]
* [https://reference.digilentinc.com/vivado Vivado - Xilinx Programming Environment - Board files, reference projects, etc]
* [https://reference.digilentinc.com/nexys:nexys4:start Nexys 4 Resource center]

==== Vivado 2015.4 Install with free licens ====

* [[Install]]

[[Category:Mikroelektronikk]]