ift - User contributions [en]

CZT-firmware

2010-10-18T19:10:44Z

Ako054: /* LED control */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''modules in control/status chain:'''
* detector module interfaces (4 -- one per chain)
* XA configuration (4 -- one per chain)
* RCU master
* bin control

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-9] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
FSM

===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

===piso8_ctrl===
FSM

==Resync register==
synchronizes the inputs and outputs of the FPGA with the internal clock signal.

==Clock reset (clkrst)==
This module generates the clock and the reset signal for the firmware components.
The signals are based on a crystal oscillator input and a global clock.

==Timetag generation (tt_gen)==
The time tag generator provides information about when an event happens. It maintains a 20-bit counter used to timestamp science events. The 20-bit time stamp then become part of the science data package (SCDP) .

CZT-firmware

2010-10-18T19:08:23Z

Ako054: /* Timetag generation (tt_gen) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''modules in control/status chain:'''
* detector module interfaces (4 -- one per chain)
* XA configuration (4 -- one per chain)
* RCU master
* bin control

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-9] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

===piso8_ctrl===
FSM

==Resync register==
synchronizes the inputs and outputs of the FPGA with the internal clock signal.

==Clock reset (clkrst)==
This module generates the clock and the reset signal for the firmware components.
The signals are based on a crystal oscillator input and a global clock.

==Timetag generation (tt_gen)==
The time tag generator provides information about when an event happens. It maintains a 20-bit counter used to timestamp science events. The 20-bit time stamp then become part of the science data package (SCDP) .

CZT-firmware

2010-10-18T19:08:08Z

Ako054: /* Clock reset (clkrst) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''modules in control/status chain:'''
* detector module interfaces (4 -- one per chain)
* XA configuration (4 -- one per chain)
* RCU master
* bin control

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-9] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

===piso8_ctrl===
FSM

==Resync register==
synchronizes the inputs and outputs of the FPGA with the internal clock signal.

==Clock reset (clkrst)==
This module generates the clock and the reset signal for the firmware components.
The signals are based on a crystal oscillator input and a global clock.

==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T19:07:48Z

Ako054: /* Resync register */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''modules in control/status chain:'''
* detector module interfaces (4 -- one per chain)
* XA configuration (4 -- one per chain)
* RCU master
* bin control

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-9] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

===piso8_ctrl===
FSM

==Resync register==
synchronizes the inputs and outputs of the FPGA with the internal clock signal.

==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T19:05:48Z

Ako054: /* Address decoder (adrdec_bgo) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''modules in control/status chain:'''
* detector module interfaces (4 -- one per chain)
* XA configuration (4 -- one per chain)
* RCU master
* bin control

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-9] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

===piso8_ctrl===
FSM

==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T18:58:43Z

Ako054: /* Memory bus interface */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

===piso8_ctrl===
FSM

==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T18:58:36Z

Ako054: /* Memory bus interface (mb_if) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
===piso8_ctrl===
FSM

==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T18:57:26Z

Ako054: /* MUX (scdp_ch_mux) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
===piso8_ctrl===
FSM

==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T18:54:21Z

Ako054: /* Binning control module (BCM) (bin_ctrl_module) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented.
There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in detector module interface

==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
===piso8_ctrl===
FSM

==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T18:52:33Z

Ako054: /* Address decoder (adrdec_bgo) */

CZT-firmware

2010-10-18T18:51:25Z

Ako054: /* Address decoder (adrdec_bgo) */

List of included modules in hierachical order:

==Detector module interface (dm_if)==
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.

===Offset substract===
Finds and subtracts the offset from ADC data, ensuring
a consistent mean value of zero between all four detector chains

===Hit discriminator (hit_dicr)===
determines whether there was an event or not?

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

==MUX (scdp_ch_mux)==
==FIFO==
==DPU interface (dpu_if) ==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

==Binning control module (BCM) (bin_ctrl_module) ==
===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
==XA config (xa_cfg)==

===XA register verification (xa_reg_verify)===
FSM, ASIC configuration register verifier
===RAM (dpram1k8)===
RAM to memorize control register, dual port RAM for volatile XA configuration data
===Memory bus interface===
===piso8_ctrl===
FSM

==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

CZT-firmware

2010-10-18T18:50:34Z

Ako054: /* DPU interface (dpu_if) */

CZT-firmware

2010-10-18T18:49:28Z

Ako054: /* Memory bus interface (mb_if) */

CZT-firmware

2010-10-18T18:48:20Z

Ako054: /* Hit discriminator (hit_dicr)= */

CZT-firmware

2010-10-18T18:47:47Z

Ako054: /* XA config (xa_cfg) */

CZT-firmware

2010-10-18T18:41:51Z

Ako054: /* Detector module interface (dm_if) */

CZT-firmware

2010-10-18T18:35:37Z

Ako054: /* Detector module interface (dm_if) */

CZT-firmware

2010-10-18T18:35:06Z

Ako054: Created page with 'List of included modules in hierachical order: ==Detector module interface (dm_if)== ==MUX (scdp_ch_mux)== ==FIFO== ==DPU interface (dpu_if) == ===xlink_rx=== ===rx register===…'

List of included modules in hierachical order:

==Detector module interface (dm_if)==
==MUX (scdp_ch_mux)==
==FIFO==
==DPU interface (dpu_if) ==
===xlink_rx===
===rx register===
===xlink_tx===
===tx register===
===tx control fsm===

==Address decoder (adrdec_bgo)==
==Binning control module (BCM) (bin_ctrl_module) ==
===Scdp channel mux===
===Bin address generator===
===Bin access control===
===Swing buffer===
===Bin module address arbiter===
===Memory bus interface (mb_if)===
==RCU master (rcumaster)==
===LED control===
===Memory bus interface (mb_if)===
==XA config (xa_cfg)==
==Resync register==
==Clock reset (clkrst)==
==Timetag generation (tt_gen)==

ASIM-CZT

2010-10-18T18:31:33Z

Ako054: /* CZT detector */

==CZT detector==

CZT stands for [http://en.wikipedia.org/wiki/Cadmium_zinc_telluride| Cadmium Zinc Telluride], a semiconductor material.
In ASIM context CZT is also the MXGS detector with imaging capability.

==Firmware==
An introduction to the CZT EBB firmware can be found here: [[CZT-firmware]]

[[Category:ASIM]]

BGO-firmware-structure

2010-10-13T14:46:20Z

Ako054: /* Memory bus interface (mb_if) */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
see [[#Memory_bus_interface_.28mb_if.29_3|mb_if ]] in Temperature Monitor

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29_3|mb_if ]] in Temperature Monitor

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

BGO-firmware-structure

2010-10-13T14:45:57Z

Ako054: /* memory bus interface (mb_if) */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===Memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29_3|mb_if ]] in Temperature Monitor

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

BGO-firmware-structure

2010-10-13T14:44:42Z

Ako054: /* memory bus interface */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in BGO channel

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===Memory bus interface (mb_if)===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

BGO-firmware-structure

2010-10-13T14:44:18Z

Ako054: /* memory bus interface */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in BGO channel

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

BGO-firmware-structure

2010-10-13T14:44:05Z

Ako054: /* memory bus interface */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in BGO channel

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

BGO-firmware-structure

2010-10-13T14:42:48Z

Ako054: /* memory bus interface (mb_if) */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface (mb_if)===
see [[#Memory_bus_interface_.28mb_if.29|mb_if ]] in BGO channel

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:39:31Z

Ako054: /* memory bus interface */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface (mb_if)===
see mb_if

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:37:52Z

Ako054: /* mb_if */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====Memory bus interface (mb_if)====
including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:37:05Z

Ako054: /* mb_if */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.
including a control register and a fsm. basically a translator.

translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:33:43Z

Ako054: /* mb_if */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.
including a control register and a fsm. basically a translator.
translating memory data into commands for active module and delivers status reports.

'''input:'''
* memory address memadr_in (from adress decoder)
* memory data memdat_in (from address decoder, incl. command )
* status register sr[0-3] (from logic module, e.g. tmon)
* clk etc.

'''output:'''
* memdat_out (to address decoder, incl. answer)
* control registers cr[0-3] (to logig module, incl. command)

general:
* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:18:10Z

Ako054: /* Temperature monitor */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor (tmon_struct)==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:17:53Z

Ako054: /* DPU interface */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface (dpu_if)==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:17:28Z

Ako054: /* Binning control module (BCM) */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM) (bin_ctrl_module)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:16:21Z

Ako054: /* Address decoder */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder (adrdec_bgo)==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:16:01Z

Ako054: /* MUX */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX (bgo_mux)==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:15:39Z

Ako054: /* BGO channel */

==BGO channel (bgo_channel_[0-2])==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:13:02Z

Ako054: /* Address decoder */

==BGO channel==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

general:
* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:12:46Z

Ako054: /* Address decoder */

==BGO channel==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
* memadr_in (from dpu_if/user)
* memdat_out_[0-4] (from modules)
* clk etc.

'''output: '''
* memadr_out (to modules)
* di_memdat_in (to dpu_if)

* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-13T14:11:56Z

Ako054: /* Address decoder */

==BGO channel==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
* the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
* delivers answer (memdat, memory data) from modules

'''input: '''
memadr_in (from dpu_if/user)
memdat_out_X (from modules)
clk etc.

'''output: '''
memadr_out (to modules)
di_memdat_in (to dpu_if)

* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-01T13:27:10Z

Ako054: /* temperature monitor */

==BGO channel==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

BGO-firmware-structure

2010-10-01T13:26:50Z

Ako054: /* temperature monitor */

==BGO channel==
There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

===PMT interface===
PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo.
tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

* mxgs_bgo_lib
* 2009 by yngve (auto)

included blocks:
====pmt_if_ctrl====
is a fsm
<pre>
port (
arst_n : in std_logic; -- asynchronous reset
rst : in std_logic; -- synchronous reset
clk : in std_logic;
diff_trig : in std_logic; -- differential trigger
ovf : in std_logic; -- ADC overflow
peak : in std_logic; -- peak found
val_trig : in std_logic; -- value trigger
fast : in std_logic; -- pulse ocurred on the tail of another pulse
offset_lock : in std_logic; -- offset is found
load : out std_logic; -- load scdp
offset_en : out std_logic; -- offset enable
acc_en : in std_logic; -- baseline correction enable
hug : out std_logic; -- release the peak hold register
par_clr : out std_logic; -- clear paralyzation flag
inhibit : in std_logic; -- inhibit further triggers
smalltrig_en : in std_logic; -- enable small triggers
adc_en : out std_logic; -- ADC enable
smpl_mode : in std_logic; -- direct sampling mode
fifo_full : in std_logic; -- fifo full flag
fifo_empty : in std_logic; -- fifo empty flag
smpl_trig : out std_logic -- feedthrough of ADC data to FIFO
);
</pre>

====mb_if====
Memory bus interface.

including a control register and a fsm

* asim_common_lib
* by yngve 2008

====mov_avrg and mov_avrg8====
moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set.
(http://en.wikipedia.org/wiki/Moving_average)

====tailgen====

pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.

====tailgen_ctrl====

is a fsm. selcting a trigger?
output= 'tg_sel' being 0 or 1

===FIFO===
stores SCDP per channel

FIFO1k48
* mxgs_bgo_lib

==MUX==
coordinates data which should be read out from fifos.
... interface to the 3 fifos included in BGO_channels

* mxgs_bgo_lib
* 2010 by magne (auto)

<pre>
port(
arst_n : in std_logic; -- asynchronous reset
clk : in std_logic; -- clock
fifo_read : in std_logic; -- read fifo from current chain
data_na : out std_logic; -- data not available
ch1_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 1
ch2_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 2
ch3_data : in std_logic_vector ( 47 downto 0 ); -- scdp from chain 3
dout : out std_logic_vector ( 47 downto 0 ); -- arbitrated data
sfifo_empty : in std_logic_vector (1 to 3);
sfifo_read : out std_logic_vector (1 to 3)
);
</pre>

==Address decoder==
memory bus address decoder and data multiplexor

* mxgs_bgo_lib
* 2008 by yngve

==Binning control module (BCM)==

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if.
-> some kind of filter

* asim_common_lib

included modules:

===scdp channel mux===
===bin address generator===
===bin access control===
===swing buffer===
===bin module address arbiter===
===memory bus interface===

==DPU interface==
is interfacing the DPU emulator, input: commands, output: data, status

* asim_common_lib

<pre>
port (
clk : in std_logic; -- clock
arst_n : in std_logic; -- asynchronous reset
memdat_in : in std_logic_vector(7 downto 0); -- memory bus data input
serial_data_in : in std_logic; -- serial data input
serial_strobe_in : in std_logic; -- serial strobe input
serial_data_out : out std_logic; -- serial data output
serial_strobe_out : out std_logic; -- serial strobe output
RnW : out std_logic; -- read / write control
ld_memdat : out std_logic; -- load memory data
memadr_out : out std_logic_vector(13 downto 0); -- memory address
memdat_out : out std_logic_vector(7 downto 0); -- memory data
scdp : in std_logic_vector(47 downto 0); -- scdp input
enable : in std_logic; -- enable input from DPU
fifo_empty : in std_logic; -- fifo empty indicator
fifo_read : out std_logic; -- fifo read enable
fifo_full : in std_logic := '0'); -- fifo full indicator

</pre>

===receiving:===
====xlink_rx====
Description: receiver for "xlink", a serial data strobe encoded point to
-- point communications protocol for the ASIM MXGS

====rx register====
reception register for DPU interface

===transmission:===

====xlink_tx====
fsm
====tx register====
transmission register for DPU interface
====tx control fsm====

==Temperature monitor==
used for temperature compensation and housekeeping
controls external MUX and a ADC.

===temperature monitor===
General description : This module is designed to control an analog mux and an ADC to capture
values from three different analog sources, in this case termistor values for temperature
meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures.
when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_bin)

* asim_common_lib

===memory bus interface===
for communication with user interface.

* asim_common_lib
* 2008 by yngve (auto)

VHDL

2010-10-01T13:15:12Z

Ako054:

==Modeling concept==
there are 3 domains of modeling:
* function
* structure
* geometry

each provides a basic modeling concept.

a module e.g. a register is an '''entity''', it's inputs ans outputs are called '''ports'''.
an '''architecture''' is the internal implementation of an entity. it describes the behavior of an entity.
architectures includes only '''processes''', collection of actions which are executed in sequences.

types of action that can be performed:
* evaluating expressions
* assigning variables and values
* conditional and repeated execution
* subprogram calls

'''''behavioral architecture''''': function of an entity is described in an abstract way. e.g.
<pre>
entity srlatch is
port ( s,r : in std_logic;
q,qb : out std_logic);
end srlatch;

architecture behave of calc is
begin
foo: process
begin
Q <= S nand QB;
QB <= R nand Q;
end process foo;
end architecture behave;
</pre>

'''''structural architecture''''': only interconnecting subsystems

<pre>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity nand2 is
port(
a,b : in std_logic;
q : out std_logic);
end nand2;

architecture basic of nand2 is
begin
q <= a nand b after 2 ns;
end basic;
</pre>

<pre>
entity srlatch is
port( s,r: in std logic;
q,qb: out std_logic);
end srlatch;

architecture struct of srlatch is
begin
sq: entity work.nand2(basic)
port map (
a => s,
b => qb,
q => q
);

rq: entity work.nand2(basic)
port map (
a => r,
b => q,
q => qb
);

end architecture struct;
</pre>

===subprograms===

subprograms are '''procedures''', a collection of statements executed for their effect, and '''functions''', a collection of statements to compute a result.

====procedures====
variables etc. defined in the header are local variables.
<pre>
procedure proc_name is
variable total : real :=0.0; --this is a local variable!
begin
for index in samples loop
total = total +sample(index);
end loop;
answer:=total;
end procedure proc_name;
</pre>

procedures without parameters is called by it's name from any place in architecture.
other procedures can also call procedures in their body.
<pre>
proc_name;
</pre>

it is possible to use procedures with parameters.

====functions====
generalization of expressions, combined values with operators and produce new values. the type of result is specified.
<pre>
function limit (val, min, max: integer) return integer is
begin
if val > max then
return max;
elseif val < min then
return min;
else
return val;
end if;
end function;
</pre>
a function is called in the architecture like this:
<pre>
newval := limit(current_val, 10, 100);
newval2 := 2 + limit(current_val, 10, 100);
</pre>

===Packages===

grouping a collection of related declarations to serve common purpose.
seperat design units that can be worked on independently, reused in different parts of design.
the can be written along with entities and architecture and are analyzed separately.
it is also possible to place a package in an other library, in that case the lib "work" has to be replaced by the lib including the package.

the external view is specified in the '''package declaration''', the implementation is defind in the '''package body'''.

====package declaration====
the package declaration hosts type, constand, subprogram, signal ... declarations which are shared within the model.
it defines the interface to a package. in the model then you just need to refer to the package:
<pre>
package yourpackagename is --declaration
constant foo: std_logic_vector(7 downto 0) := X"01";
type foobar is array (foobar2) of somethingelse;
end package yourpackagename;
</pre>
<pre>
use yourpackagename.all;

entity yourentityname is
port (
fooport : in work.yourpackagename.foo;
foobarport : in work.yourpackagename.foobar;
);
end entity yourentityname;
</pre>

====package body====
no package body is needed if pkg declaration contains other kinds of declarations like types, signals or fully specified constants. in case of subprograms body needed to fill in missing informations.

items declared in body must include full declaration of subprograms as they are in the pkg declaration. that means that types, modes, default constants... must bee repeated exactly.

===components===
to build hierarchical designs, used to describe interconnections in subsystems in a design.
component declarations are written in the declarative part of the architecture (before the ''begin'').
it is an alternative to use entity declarations (see structural design).
an entity declaration defines a real module, it's a separate design. a component declaration defines a virtual module in the architecture body. "for this architecture we assume there is a module specified by this component".

===configurations===
in a configuration file the declaration can be made in which case which entity is using which architecture. the architectures may vary e.g. in case of simulation or synthesis.
A '''configuration declaration''' is a design unit which can be compiled separately. In a configuration declaration the binding of all components which are part of a certain entity can be specified.
also generic maps can be set.

<pre>
configuration config_identifier of entity_name is
for architecture_name

for all : component_identifier
use entity lib_name.entity_name2(architecture_name2); --binding_indication
end for;

for bgo_channel_1 : bgo_channel
use entity mxgs_bgo_lib.bgo_channel(struct)
generic map(
g_bgo_channel => "01"
);
end for;

end for;
end config_identifier;

</pre>

VHDL

2010-10-01T12:31:01Z

Ako054: /* components */

==Modeling concept==
there are 3 domains of modeling:
* function
* structure
* geometry

each provides a basic modeling concept.

a module e.g. a register is an '''entity''', it's inputs ans outputs are called '''ports'''.
an '''architecture''' is the internal implementation of an entity. it describes the behavior of an entity.
architectures includes only '''processes''', collection of actions which are executed in sequences.

types of action that can be performed:
* evaluating expressions
* assigning variables and values
* conditional and repeated execution
* subprogram calls

'''''behavioral architecture''''': function of an entity is described in an abstract way. e.g.
<pre>
entity srlatch is
port ( s,r : in std_logic;
q,qb : out std_logic);
end srlatch;

architecture behave of calc is
begin
foo: process
begin
Q <= S nand QB;
QB <= R nand Q;
end process foo;
end architecture behave;
</pre>

'''''structural architecture''''': only interconnecting subsystems

<pre>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity nand2 is
port(
a,b : in std_logic;
q : out std_logic);
end nand2;

architecture basic of nand2 is
begin
q <= a nand b after 2 ns;
end basic;
</pre>

<pre>
entity srlatch is
port( s,r: in std logic;
q,qb: out std_logic);
end srlatch;

architecture struct of srlatch is
begin
sq: entity work.nand2(basic)
port map (
a => s,
b => qb,
q => q
);

rq: entity work.nand2(basic)
port map (
a => r,
b => q,
q => qb
);

end architecture struct;
</pre>

===subprograms===

subprograms are '''procedures''', a collection of statements executed for their effect, and '''functions''', a collection of statements to compute a result.

====procedures====
variables etc. defined in the header are local variables.
<pre>
procedure proc_name is
variable total : real :=0.0; --this is a local variable!
begin
for index in samples loop
total = total +sample(index);
end loop;
answer:=total;
end procedure proc_name;
</pre>

procedures without parameters is called by it's name from any place in architecture.
other procedures can also call procedures in their body.
<pre>
proc_name;
</pre>

it is possible to use procedures with parameters.

====functions====
generalization of expressions, combined values with operators and produce new values. the type of result is specified.
<pre>
function limit (val, min, max: integer) return integer is
begin
if val > max then
return max;
elseif val < min then
return min;
else
return val;
end if;
end function;
</pre>
a function is called in the architecture like this:
<pre>
newval := limit(current_val, 10, 100);
newval2 := 2 + limit(current_val, 10, 100);
</pre>

===Packages===

grouping a collection of related declarations to serve common purpose.
seperat design units that can be worked on independently, reused in different parts of design.
the can be written along with entities and architecture and are analyzed separately.
it is also possible to place a package in an other library, in that case the lib "work" has to be replaced by the lib including the package.

the external view is specified in the '''package declaration''', the implementation is defind in the '''package body'''.

====package declaration====
the package declaration hosts type, constand, subprogram, signal ... declarations which are shared within the model.
it defines the interface to a package. in the model then you just need to refer to the package:
<pre>
package yourpackagename is --declaration
constant foo: std_logic_vector(7 downto 0) := X"01";
type foobar is array (foobar2) of somethingelse;
end package yourpackagename;
</pre>
<pre>
use yourpackagename.all;

entity yourentityname is
port (
fooport : in work.yourpackagename.foo;
foobarport : in work.yourpackagename.foobar;
);
end entity yourentityname;
</pre>

====package body====
no package body is needed if pkg declaration contains other kinds of declarations like types, signals or fully specified constants. in case of subprograms body needed to fill in missing informations.

items declared in body must include full declaration of subprograms as they are in the pkg declaration. that means that types, modes, default constants... must bee repeated exactly.

===components===
to build hierarchical designs, used to describe interconnections in subsystems in a design.
component declarations are written in the declarative part of the architecture (before the ''begin'').
it is an alternative to use entity declarations (see structural design).
an entity declaration defines a real module, it's a separate design. a component declaration defines a virtual module in the architecture body. "for this architecture we assume there is a module specified by this component".

===configurations===
in a configuration file the declaration can be made in which case which entity is using which architecture. the architectures may vary e.g. in case of simulation or synthesis.
A '''configuration declaration''' is a design unit which can be compiled separately. In a configuration declaration the binding of all components which are part of a certain entity can be specified.

<pre>
configuration config_identifier of entity_name is
for architecture_name

for all : component_identifier
use entity lib_name.entity_name2(architecture_name2); --binding_indication
end for;

for bgo_channel_1 : bgo_channel
use entity mxgs_bgo_lib.bgo_channel(struct)
generic map(
g_bgo_channel => "01"
);
end for;

end for;
end config_identifier;

</pre>

VHDL

2010-09-29T14:27:33Z

Ako054:

VHDL

2010-09-29T14:10:18Z

Ako054: /* components */

VHDL

2010-09-29T13:55:01Z

Ako054:

VHDL

2010-09-29T13:30:29Z

Ako054:

VHDL

2010-09-29T13:29:46Z

Ako054:

VHDL

2010-09-29T09:41:49Z

Ako054:

VHDL

2010-09-28T17:50:22Z

Ako054:

VHDL

2010-09-28T16:31:16Z

Ako054: