Spice deck: Difference between revisions
(Created page with '<pre> Common Source gain stage, max gain * Analysis and design of analog integrated circuits * Problem 3.4 * NB ! Model level 1 only - Similar to hand calcualtions * * Voltage ...') |
No edit summary |
||
Line 1: | Line 1: | ||
<pre> | <pre> | ||
Common Source gain stage, max gain | |||
* Analysis and design of analog integrated circuits | * Analysis and design of analog integrated circuits | ||
* Problem 3.4 | * Problem 3.4 | ||
Line 25: | Line 25: | ||
* Models | * Models | ||
* | * | ||
.model nmos nmos level=1 VT0=0.6 KP=200u LAMBDA=0 | .model nmos nmos (level=1 VT0=0.6 KP=200u LAMBDA=0.2 | ||
+ TOX=10e-9 PHI=0.93 GAMMA=0.6 | |||
+ CJ=9.8E-5 PB=0.72 MJ=0.36 | |||
+ CJSW=2.2E-10 MJSW=0.1) | |||
* | * | ||
* Setup | * Setup |
Revision as of 08:57, 29 September 2009
Common Source gain stage, max gain * Analysis and design of analog integrated circuits * Problem 3.4 * NB ! Model level 1 only - Similar to hand calcualtions * * Voltage * from to volts VDD VDD VSS 3 * Transistor * Drain Gate Source Bulk MN1 Out In VSS VSS nmos W=10u L=1u * Load Resistor and Capacitor * from to ohms RD VDD Out 5k Cl Out VSS 0.1p * Voltage source * from to volts VI In VSS DC 1.281 AC 1 * * Models * .model nmos nmos (level=1 VT0=0.6 KP=200u LAMBDA=0.2 + TOX=10e-9 PHI=0.93 GAMMA=0.6 + CJ=9.8E-5 PB=0.72 MJ=0.36 + CJSW=2.2E-10 MJSW=0.1) * * Setup * .options nomod nopage .width OUT=80 .connect vss 0 * * Simulation and Plots * *.TF V(Out) VI *.OP .ac dec 10 1k 100.0e9 * Amplitude Bode Plot .plot ac vdb(Out) * Phase Bode Plot .plot ac vp(Out) .END